公开(公告)号：US12243855B2

公开(公告)日：2025-03-04

申请号：US17532754

申请日：2021-11-22

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Durodami Lisk ,  Hong Bok We ,  Charles David Paynter

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

公开(公告)号：US11658391B2

公开(公告)日：2023-05-23

申请号：US17129084

申请日：2020-12-21

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Jeahyeong Han ,  Mohammad Ali Tassoudji

IPC: H01Q1/52 ,  H01Q21/00 ,  H01Q23/00 ,  H01Q1/22

CPC classification number: H01Q1/2283 ,  H01Q1/526 ,  H01Q21/0087 ,  H01L2223/6677 ,  H01Q23/00

Abstract: Aspects disclosed herein include a device including a first antenna substrate including one or more antennas. The device also includes a metallization structure. The device also includes a first spacer disposed between the first antenna substrate and the metallization structure, configured to maintain a constant distance between the first antenna substrate and the metallization structure. The device also includes a first plurality of conductive elements, disposed within the first spacer, configured to electrically couple the first antenna substrate to the metallization structure. The device also includes where the first spacer is configured to enclose all the conductive elements, electrically coupled to the first antenna substrate, and is configured to form an air gap between the first antenna substrate and the metallization structure. The device also includes where the first plurality of conductive elements is separated by air in the air gap.

公开(公告)号：US11562962B2

公开(公告)日：2023-01-24

申请号：US17148367

申请日：2021-01-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

Abstract: A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

公开(公告)号：US11551939B2

公开(公告)日：2023-01-10

申请号：US17010693

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

公开(公告)号：US20220278016A1

公开(公告)日：2022-09-01

申请号：US17188236

申请日：2021-03-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Bohan Yan

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.

公开(公告)号：US11289453B2

公开(公告)日：2022-03-29

申请号：US16803804

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Zhijie Wang ,  Hong Bok We

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A package comprising a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure and the substrate are coupled together in such a way that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels through at least the substrate, then through the interconnect structure and back through the substrate.

公开(公告)号：US20170243845A1

公开(公告)日：2017-08-24

申请号：US15048906

申请日：2016-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/3105

CPC classification number: H01L24/14 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects couple to pads on an encapsulated die. The interconnects have a pad-facing surface that couples to a corresponding pad through a seed layer. The seed layer does not cover the sidewalls of the interconnects.

公开(公告)号：US09642259B2

公开(公告)日：2017-05-02

申请号：US14067677

申请日：2013-10-30

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Dong Wook Kim ,  Hong Bok We

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H05K1/11 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

公开(公告)号：US09633977B1

公开(公告)日：2017-04-25

申请号：US15040902

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Shiqun Gu ,  Urmi Ray ,  Ratibor Radojcic

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/10 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/92144 ,  H01L2924/19105 ,  H05K1/14 ,  H05K1/148 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

公开(公告)号：US09595496B2

公开(公告)日：2017-03-14

申请号：US14535966

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/02 ,  H01L21/44 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分配部分的集成器件封装。 封装部分包括第一管芯，耦合到第一管芯的第一组通孔，第二管芯，耦合到第二管芯的第二组通孔，桥接器和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一个模具。 桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分地封装第一管芯，第二管芯，桥接器，第一组通孔和第二组通孔。 再分配部分耦合到封装部分。 再分配部分包括一组再分布互连和至少一个电介质层。