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1.发明申请METHOD FOR WRTITING DATA, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT 有权数据记录方法，存储器存储器和存储器控制电路单元公开(公告)号：US20150242122A1
公开(公告)日：2015-08-27
申请号：US14253886
申请日：2014-04-16
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh , Li-Chun Liang
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/00 , G06F12/00 , G06F12/0246 , G06F2206/1014
Abstract: A method for writing data, a memory storage device and a memory control circuit unit are provided. The method includes receiving a write command and first data corresponding to the write command, obtaining initial data transmission information of the first data and determining whether the initial data transmission information conforms to a predetermined condition, compressing the first data to second data and writing the second data into a rewritable non-violate memory module if the initial data transmission information conforms to the predetermined condition, and writing the uncompressed first data into the rewritable non-violate memory module if the initial data transmission information does not conform to the predetermined condition.
Abstract translation: 提供一种写入数据的方法，存储器存储装置和存储器控制电路单元。 该方法包括接收写入命令和对应于写入命令的第一数据，获得第一数据的初始数据传输信息，并确定初始数据传输信息是否符合预定条件，将第一数据压缩为第二数据并写入第二数据 如果初始数据传输信息符合预定条件，则将数据转换成可重写的非违规存储器模块，如果初始数据传输信息不符合预定条件，则将未压缩的第一数据写入可重写的非违规存储器模块。
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公开(公告)号：US10983858B2
公开(公告)日：2021-04-20
申请号：US16586911
申请日：2019-09-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang
Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.
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3.发明授权Data managing method, memory control circuit unit and memory storage apparatus 有权数据管理方法，存储器控制电路单元和存储器存储装置公开(公告)号：US09431132B2
公开(公告)日：2016-08-30
申请号：US14307509
申请日：2014-06-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Kuo-Hsin Lai , Pei-Yu Shih , Tien-Ching Wang
CPC classification number: G11C29/52 , G06F11/1012 , G06F11/106 , G06F11/1068 , G06F11/1076 , G11B20/1833 , G11C2029/0411
Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.
Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。
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4.发明申请ERROR PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT 审中-公开错误处理方法，存储器存储器件和存储器控制电路单元公开(公告)号：US20160098316A1
公开(公告)日：2016-04-07
申请号：US14565437
申请日：2014-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Shao-Wei Yen , Tien-Ching Wang , Yu-Hsiang Lin , Kuo-Hsin Lai , Li-Chun Liang
CPC classification number: G06F11/1068 , G06F11/1012 , G11C11/5642 , G11C16/349 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0409
Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
Abstract translation: 提供了一种用于可重写非易失性存储器模块，存储器存储装置和存储器控制电路单元的错误处理方法。 可重写非易失性存储器模块包括多个存储单元。 该错误处理方法包括：从存储器单元发送用于读取多个位的第一读取命令序列; 对比特执行第一解码; 如果所述比特具有至少一个错误，则确定每个错误是否属于第一类型错误或第二类型错误; 如果所述第一错误属于所述第一类型错误，则记录所述至少一个错误中的第一错误的相关信息; 并且如果第一错误属于第二类型错误，则不记录第一错误的相关信息。 因此，可以适当地处理特定类型的错误。
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公开(公告)号：US20210049064A1
公开(公告)日：2021-02-18
申请号：US16586911
申请日：2019-09-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang
Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.
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Patent Agency Ranking
6.发明申请MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF 有权存储器存储器件，其存储器控制器及其处理数据的方法公开(公告)号：US20140047300A1
公开(公告)日：2014-02-13
申请号：US13662541
申请日：2012-10-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Tien-Ching Wang , Kuo-Hsin Lai
IPC: H03M13/13
CPC classification number: G06F11/1008 , G06F11/1044 , G06F11/1068 , G11C7/1006 , H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/2778 , H03M13/2906
Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.
Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。
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公开(公告)号：US10067824B2
公开(公告)日：2018-09-04
申请号：US14565437
申请日：2014-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Shao-Wei Yen , Tien-Ching Wang , Yu-Hsiang Lin , Kuo-Hsin Lai , Li-Chun Liang
Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.
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公开(公告)号：US09690490B2
公开(公告)日：2017-06-27
申请号：US14253886
申请日：2014-04-16
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh , Li-Chun Liang
CPC classification number: G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/00 , G06F12/00 , G06F12/0246 , G06F2206/1014
Abstract: A method for writing data, a memory storage device and a memory control circuit unit are provided. The method includes receiving a write command and first data corresponding to the write command, obtaining initial data transmission information of the first data and determining whether the initial data transmission information conforms to a predetermined condition, compressing the first data to second data and writing the second data into a rewritable non-violate memory module if the initial data transmission information conforms to the predetermined condition, and writing the uncompressed first data into the rewritable non-violate memory module if the initial data transmission information does not conform to the predetermined condition.
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9.发明授权Memory storage device, memory controller thereof, and method for processing data thereof 有权存储器存储装置，其存储器控制器及其数据处理方法公开(公告)号：US09223648B2
公开(公告)日：2015-12-29
申请号：US13662541
申请日：2012-10-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Tien-Ching Wang , Kuo-Hsin Lai
CPC classification number: G06F11/1008 , G06F11/1044 , G06F11/1068 , G11C7/1006 , H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/2778 , H03M13/2906
Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.
Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。
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10.发明申请DATA MANAGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS 有权数据管理方法，存储器控制电路单元和存储器存储器公开(公告)号：US20150331742A1
公开(公告)日：2015-11-19
申请号：US14307509
申请日：2014-06-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Li-Chun Liang , Kuo-Hsin Lai , Pei-Yu Shih , Tien-Ching Wang
CPC classification number: G11C29/52 , G06F11/1012 , G06F11/106 , G06F11/1068 , G06F11/1076 , G11B20/1833 , G11C2029/0411
Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.
Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。
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