公开(公告)号：US12125517B2

公开(公告)日：2024-10-22

申请号：US17804414

申请日：2022-05-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20240192862A1

公开(公告)日：2024-06-13

申请号：US18582356

申请日：2024-02-20

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

摘要： Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

公开(公告)号：US20240176697A1

公开(公告)日：2024-05-30

申请号：US18521600

申请日：2023-11-28

申请人： Micron Technology, Inc.

发明人： Smruti Subhash Jhaveri ,  Hyun Yoo Lee

IPC分类号： G06F11/10 ,  G06F13/42

CPC分类号： G06F11/1016 ,  G06F11/1068 ,  G06F13/4221

摘要： Described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. Each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. If a memory die has more faults than spare rows, the memory die cannot repair the additional faults. This document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. The controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. The controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.

公开(公告)号：US20240170091A1

公开(公告)日：2024-05-23

申请号：US18511440

申请日：2023-11-16

申请人： Micron Technology, Inc.

发明人： Yoshiro Riho ,  Hyun Yoo Lee ,  Yang Lu

IPC分类号： G11C29/52 ,  G11C7/08 ,  G11C7/10

CPC分类号： G11C29/52 ,  G11C7/08 ,  G11C7/1039

摘要： Described apparatuses and methods provide system error correction code (ECC) circuitry routing that segregates even sense amp (SA) line data sets and odd SA line data sets in a memory, such as a low-power dynamic random-access memory. A memory device may include one or more dies, and a die can have even SA line data sets and odd SA line data sets. The memory device may also include ECC circuitry comprising one or more ECC engines. By segregating the data sets, instead of coupling even and odd SA line data sets to a single ECC engine, double-bit errors on a single word line may be separated into two single-bit errors. Thus, by utilizing system ECC circuitry routing in this way, even a one-bit ECC algorithm may be used to correct double bits, which may increase data reliability.

公开(公告)号：US20240161796A1

公开(公告)日：2024-05-16

申请号：US18420404

申请日：2024-01-23

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC分类号： G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

CPC分类号： G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

摘要： Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US11868650B2

公开(公告)日：2024-01-09

申请号：US17662993

申请日：2022-05-11

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4096 ,  G11C2211/4062

摘要： Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US11783885B2

公开(公告)日：2023-10-10

申请号：US17513090

申请日：2021-10-28

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee

IPC分类号： G11C11/406 ,  G11C7/10

CPC分类号： G11C11/40615 ,  G11C7/1009 ,  G11C11/40618 ,  G11C11/40622

摘要： Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM), and an associated host device are described. The memory device includes control circuitry that can determine an operational status of the memory device (e.g., whether the memory device is currently performing a self-refresh operation). The control circuitry can also transmit a signal indicative of the operational status to the host device in response to receiving a command directing the memory device to exit a self-refresh mode. The host device can operate based on the signal. The signal may therefore allow the memory device, the host device, or both to manage operations, including whether to send, receive, or process commands and data read/write requests during times that may be associated with self-refresh operations.

公开(公告)号：US11783883B2

公开(公告)日：2023-10-10

申请号：US17459446

申请日：2021-08-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee

IPC分类号： G11C11/00 ,  G11C11/406

CPC分类号： G11C11/40615

摘要： Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.

公开(公告)号：US20220209998A1

公开(公告)日：2022-06-30

申请号：US17562588

申请日：2021-12-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC分类号： H04L25/03 ,  H04L25/49

摘要： Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：US20220066655A1

公开(公告)日：2022-03-03

申请号：US17460013

申请日：2021-08-27

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/06

摘要： Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.