公开(公告)号：US20150087142A1

公开(公告)日：2015-03-26

申请号：US14555182

申请日：2014-11-26

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jong-Won LIM ,  Ho Kyun AHN ,  Young Rak PARK ,  Dong Min KANG ,  Woo Jin CHANG ,  Seong-il KIM ,  Sung Bum BAE ,  Sang-Heung LEE ,  Hyung Sup YOON ,  Chull Won JU ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66431 ,  H01L21/28255 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7787

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。

公开(公告)号：US20160020147A1

公开(公告)日：2016-01-21

申请号：US14862123

申请日：2015-09-22

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jongmin LEE ,  Byoung-Gue MIN ,  Seong-il KIM ,  Hyung Sup YOON ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L21/8222 ,  H01L27/06

CPC classification number: H01L21/8222 ,  H01G7/00 ,  H01L27/0647 ,  H01L27/0658 ,  H01L29/93 ,  H03F1/565 ,  H03F3/21 ,  H03F2200/36 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03H7/38 ,  Y10T29/43

Abstract: A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.

Abstract translation: 一种可变电容器的制造方法，包括：形成电容值取决于施加到基板上的第一区域的两端的电压的第一元件，形成具有固定在第二区域上的电容值的第二元件 基板，与第一区域相邻，并且形成用于连接第一元件和第二元件的金属线，并且将第一元件和第二元件与外部连接。 第一个元件可以是可以包括二极管的双极晶体管。 第二元件可以是包括电介质的电容器。

公开(公告)号：US20180145684A1

公开(公告)日：2018-05-24

申请号：US15654792

申请日：2017-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojin CHANG ,  Jong-Won LIM ,  Dong Min KANG ,  Dong-Young KIM ,  Seong-il KIM ,  Hae Cheon KIM ,  Jae Won DO ,  BYOUNG-GUE MIN ,  Min Jeong SHIN ,  Hokyun AHN ,  Hyung Sup YOON ,  Sang-Heung LEE ,  JONGMIN LEE ,  Sungjae CHANG ,  Yoo Jin JANG ,  HYUNWOOK JUNG ,  Kyu Jun CHO ,  Hong Gu JI

IPC: H03K17/687 ,  H03K17/693 ,  G11C5/14 ,  H03K19/0175 ,  H03K3/353

CPC classification number: H03K17/687 ,  G11C5/14 ,  H03K3/353 ,  H03K17/08122 ,  H03K17/102 ,  H03K17/122 ,  H03K17/145 ,  H03K17/162 ,  H03K17/28 ,  H03K17/693 ,  H03K19/0175

Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.