公开(公告)号：US12075628B2

公开(公告)日：2024-08-27

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US11069853B2

公开(公告)日：2021-07-20

申请号：US16195313

申请日：2018-11-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-Wei Tseng ,  Chando Park ,  Jaesoo Ahn ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US10255935B2

公开(公告)日：2019-04-09

申请号：US15862301

申请日：2018-01-04

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala ,  Rongjun Wang

IPC: H01L27/20 ,  G11B5/39 ,  G11B5/31 ,  G11C11/15 ,  H01L21/768

Abstract: Embodiments herein provide film stacks utilized to form a magnetic tunnel junction (MTJ) structure on a substrate, comprising: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer, wherein the capping layer comprises one or more layers; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru.

公开(公告)号：US11552244B2

公开(公告)日：2023-01-10

申请号：US17193966

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Rongjun Wang ,  Mahendra Pakala

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US11522126B2

公开(公告)日：2022-12-06

申请号：US16601250

申请日：2019-10-14

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Sahil Patel ,  Chando Park ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  G11B5/39 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

Abstract: A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

公开(公告)号：US10923652B2

公开(公告)日：2021-02-16

申请号：US16448709

申请日：2019-06-21

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  C23C14/54 ,  H01F10/32 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  H01L21/67 ,  H01F10/13

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US10756259B2

公开(公告)日：2020-08-25

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Chando Park ,  Hsin-wei Tseng ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/00 ,  H01L43/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US10586914B2

公开(公告)日：2020-03-10

申请号：US15712185

申请日：2017-09-22

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Sajjad Amin Hassan ,  Mahendra Pakala ,  Jaesoo Ahn

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.

公开(公告)号：US11818959B2

公开(公告)日：2023-11-14

申请号：US17379780

申请日：2021-07-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei Tseng ,  Chando Park ,  Jaesoo Ahn ,  Lin Xue ,  Mahendra Pakala

IPC: H10N50/85 ,  H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US11723283B2

公开(公告)日：2023-08-08

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/095 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.