公开(公告)号：US20240088222A1

公开(公告)日：2024-03-14

申请号：US17943137

申请日：2022-09-12

Applicant: Applied Materials, Inc.

Inventor： Shawn THOMAS ,  Saurabh CHOPRA ,  John TOLLE

IPC: H01L29/08 ,  C23C16/22 ,  C23C16/56 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  C23C16/22 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02661 ,  H01L21/02672 ,  H01L21/02675 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer within the trench.

公开(公告)号：US20240018658A1

公开(公告)日：2024-01-18

申请号：US18085371

申请日：2022-12-20

Applicant: Applied Materials, Inc.

Inventor： Zuoming ZHU ,  Ala MORADIAN ,  Shu-Kwan LAU ,  John TOLLE ,  Manjunath SUBBANNA ,  Martin Jeffrey SALINAS ,  Chia Cheng CHIN ,  Thomas KIRSCHENHEITER ,  Saurabh CHOPRA

IPC: C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C30B25/14 ,  C30B25/12 ,  C30B25/10 ,  C30B25/08

CPC classification number: C23C16/45591 ,  C23C16/458 ,  C23C16/46 ,  C30B25/14 ,  C30B25/12 ,  C30B25/10 ,  C30B25/08

Abstract: The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.

公开(公告)号：US20240274464A1

公开(公告)日：2024-08-15

申请号：US18108272

申请日：2023-02-10

Applicant: Applied Materials, Inc.

Inventor： Matthew Gabriel GOODMAN ,  John TOLLE ,  Shawn THOMAS ,  Lori D. WASHINGTON ,  Xinning LUAN ,  Zhepeng CONG

IPC: H01L21/687

CPC classification number: H01L21/68757 ,  H01L21/68785

Abstract: A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

公开(公告)号：US20240145241A1

公开(公告)日：2024-05-02

申请号：US18383100

申请日：2023-10-24

Applicant: Applied Materials, Inc.

Inventor： Joe MARGETIS ,  John TOLLE ,  Shawn THOMAS

IPC: H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/3065

Abstract: Method of forming a semiconductor device are provided. In some implementations, the method includes positioning a substrate into a processing chamber, the substrate having an exposed non-crystalline surface and an exposed crystalline surface. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pre-treatment gas into the processing chamber. The pre-treatment gas comprises a molecule that acts to lower interfacial energy between the exposed non-crystalline surface and the exposed crystalline surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

公开(公告)号：US20240038531A1

公开(公告)日：2024-02-01

申请号：US18098547

申请日：2023-01-18

Applicant: Applied Materials, Inc.

Inventor： Thomas KIRSCHENHEITER ,  John TOLLE ,  Abhishek DUBE ,  Maribel MALDONADO-GARCIA

IPC: H01L21/02 ,  H01L21/304 ,  H10B12/00

CPC classification number: H01L21/02532 ,  H01L21/02507 ,  H01L21/0245 ,  H01L21/0206 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/304 ,  H10B12/02 ,  H10B12/30

Abstract: A method and apparatus for forming strain relaxed buffers that may be used in semiconductor devices incorporating superlattice structures are provided. The method includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first surface that contacts a frontside surface of the substrate and a second surface opposite the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.

公开(公告)号：US20230029344A1

公开(公告)日：2023-01-26

申请号：US17870327

申请日：2022-07-21

Applicant: Applied Materials, Inc.

Inventor： John TOLLE ,  Thomas KIRSCHENHEITER ,  Joe MARGETIS ,  Patricia M. LIU ,  Zuoming ZHU ,  Flora Fong-Song CHANG

IPC: H01L29/15 ,  H01L21/02 ,  H01L29/10

Abstract: A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.