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1.发明申请公开(公告)号：US20160300813A1
公开(公告)日：2016-10-13
申请号：US14680539
申请日：2015-04-07
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu , Chonghua Zhong , Mengzhi Pang , Se Young Yang
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/561 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13144 , H01L2224/16227 , H01L2224/73204 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/06558 , H01L2225/06572 , H01L2225/06586 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , H01L2224/81 , H01L2924/014 , H01L2224/83
Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.
Abstract translation: 描述了包装和形成方法。 在一个实施例中，包装包括直接形成在顶模上的再分配层（RDL）和安装在RDL的后表面上的底模。
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公开(公告)号：US20150303149A1
公开(公告)日：2015-10-22
申请号：US14331363
申请日：2014-07-15
Applicant: Apple Inc.
Inventor： Jun Zhai , Mengzhi Pang , Se Young Yang , Leland W. Lew
IPC: H01L23/552 , H01L23/367 , H01L25/18 , H01L23/00 , H01L25/00 , H01L25/065
CPC classification number: H01L23/552 , H01L21/561 , H01L23/3128 , H01L23/367 , H01L23/3675 , H01L23/49805 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/16145 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73257 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06589 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/01029 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2224/81
Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.
Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 第一衬底可以包括电连接组件的第一组电导体。 在一些实施例中，组件可以包括耦合到第一衬底的至少一个电导体，使得电导体中的至少一个暴露于半导体器件封装组件的周边表面。 在一些实施例中，组件可以包括使用第二组电导体电连接到第一衬底的第二表面的第一裸片。 组件可以包括耦合到第一管芯的电子存储器模块。 在一些实施例中，组件可以包括施加到组件的上表面并且电耦合到暴露的电导体中的至少一个的屏蔽。 在使用过程中，屏蔽可能会阻碍电磁干扰。
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公开(公告)号：US20160260684A1
公开(公告)日：2016-09-08
申请号：US14638925
申请日：2015-03-04
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu , Kwan-Yu Lai , Mengzhi Pang , Chonghua Zhong , Se Young Yang
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L25/0652 , H01L21/568 , H01L23/3135 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/50 , H01L2224/04105 , H01L2224/08167 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/27318 , H01L2224/2732 , H01L2224/27436 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/81193 , H01L2224/83191 , H01L2224/83855 , H01L2224/83862 , H01L2224/83874 , H01L2224/92244 , H01L2224/94 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06572 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1461 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2224/27 , H01L2924/014
Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.
Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。
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公开(公告)号：US20180204820A1
公开(公告)日：2018-07-19
申请号：US15408263
申请日：2017-01-17
Applicant: Apple Inc.
Inventor： Jun Zhai , Chonghua Zhong , Kunzhong Hu , Se Young Yang
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L23/31 , H01L25/18 , H01L21/48 , H01L21/56 , H01L25/00 , H01L21/768 , H01L21/683 , H01L21/78
CPC classification number: H01L25/0657 , G11C11/005 , G11C14/0018 , H01L21/4857 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/76885 , H01L21/78 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2221/68359 , H01L2224/16225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48225 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06586 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443 , H01L2924/15311
Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.
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Patent Agency Ranking
公开(公告)号：US09633974B2
公开(公告)日：2017-04-25
申请号：US14638925
申请日：2015-03-04
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu , Kwan-Yu Lai , Mengzhi Pang , Chonghua Zhong , Se Young Yang
IPC: H01L25/065 , H01L25/00 , H01L23/31 , H01L21/56 , H01L23/538 , H01L23/00
CPC classification number: H01L25/0652 , H01L21/568 , H01L23/3135 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/50 , H01L2224/04105 , H01L2224/08167 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/27318 , H01L2224/2732 , H01L2224/27436 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/81193 , H01L2224/83191 , H01L2224/83855 , H01L2224/83862 , H01L2224/83874 , H01L2224/92244 , H01L2224/94 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06572 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1461 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2224/27 , H01L2924/014
Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.
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公开(公告)号：US10181455B2
公开(公告)日：2019-01-15
申请号：US15408263
申请日：2017-01-17
Applicant: Apple Inc.
Inventor： Jun Zhai , Chonghua Zhong , Kunzhong Hu , Se Young Yang
IPC: H01L21/48 , H01L25/065 , H01L23/00 , H01L23/498 , H01L23/31 , H01L25/18 , H01L21/56 , H01L25/00 , H01L21/768 , H01L21/683 , H01L21/78 , G11C14/00
Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.
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公开(公告)号：US09659907B2
公开(公告)日：2017-05-23
申请号：US14680539
申请日：2015-04-07
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu , Chonghua Zhong , Mengzhi Pang , Se Young Yang
IPC: H01L23/48 , H01L25/065 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/561 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13144 , H01L2224/16227 , H01L2224/73204 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/06558 , H01L2225/06572 , H01L2225/06586 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , H01L2224/81 , H01L2924/014 , H01L2224/83
Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.
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8.发明申请RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USING SAME 审中-公开重构的宽I / O存储器模块和使用相同的包装架构公开(公告)号：US20150364454A1
公开(公告)日：2015-12-17
申请号：US14558906
申请日：2014-12-03
Applicant: Apple Inc.
Inventor： Jun Zhai , Chonghua Zhong , Kunzhong Hu , Se Young Yang
IPC: H01L25/18 , H01L23/00 , H01L23/528 , H01L23/31 , H01L23/367 , H01L25/065 , H01L23/522
CPC classification number: H01L25/18 , H01L23/3128 , H01L23/36 , H01L23/49811 , H01L23/49816 , H01L23/5384 , H01L24/17 , H01L24/20 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17051 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
Abstract: In some embodiments, it is desirable to increase memory bandwidth using an integrated solution. In one embodiment, wide I/O memory may be used. Described herein are embodiments of systems and methods of reconfiguring wide I/O memory modules. The reconfigured memory modules may be configured such that the memory modules function in combination with current packaging architectures.
Abstract translation: 在一些实施例中，期望使用集成解决方案来增加存储器带宽。 在一个实施例中，可以使用宽I / O存储器。 这里描述了重新配置宽I / O存储器模块的系统和方法的实施例。 重新配置的存储器模块可以被配置为使得存储器模块与当前的封装体系结合起来。
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公开(公告)号：US09236355B2
公开(公告)日：2016-01-12
申请号：US14331363
申请日：2014-07-15
Applicant: Apple Inc.
Inventor： Jun Zhai , Mengzhi Pang , Se Young Yang , Leland W. Lew
IPC: H01L23/60 , H01L23/538 , H01L23/485 , H01L23/552 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/367
CPC classification number: H01L23/552 , H01L21/561 , H01L23/3128 , H01L23/367 , H01L23/3675 , H01L23/49805 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/16145 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73257 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06589 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/01029 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2224/81
Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.
Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 第一衬底可以包括电连接组件的第一组电导体。 在一些实施例中，组件可以包括耦合到第一衬底的至少一个电导体，使得电导体中的至少一个暴露于半导体器件封装组件的周边表面。 在一些实施例中，组件可以包括使用第二组电导体电连接到第一衬底的第二表面的第一裸片。 组件可以包括耦合到第一管芯的电子存储器模块。 在一些实施例中，组件可以包括施加到组件的上表面并且电耦合到暴露的电导体中的至少一个的屏蔽。 在使用过程中，屏蔽可能会阻碍电磁干扰。
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