公开(公告)号：US20160086678A1

公开(公告)日：2016-03-24

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。

公开(公告)号：US20200319248A1

公开(公告)日：2020-10-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  G01R31/3177 ,  H03M1/12

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US20170084349A1

公开(公告)日：2017-03-23

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US10026499B2

公开(公告)日：2018-07-17

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C7/00 ,  G11C8/00 ,  G11C29/56

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US09514842B2

公开(公告)日：2016-12-06

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/56

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。

公开(公告)号：US20240393394A1

公开(公告)日：2024-11-28

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

公开(公告)号：US09892802B1

公开(公告)日：2018-02-13

申请号：US14714381

申请日：2015-05-18

Applicant: Apple Inc.

Inventor： Bo Yang ,  Andrew J. Copperhall ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/10 ,  G01R31/3177 ,  G11C29/50

CPC classification number: G11C29/10 ,  G01R31/3177

Abstract: A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

公开(公告)号：US20160291625A1

公开(公告)日：2016-10-06

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

公开(公告)号：US09234942B2

公开(公告)日：2016-01-12

申请号：US13624372

申请日：2012-09-21

Applicant: Apple Inc.

Inventor： Anuja Banerjee ,  Samy R. Makar ,  Vijay M. Bettada

IPC: G01R31/3185

CPC classification number: G01R31/318594

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract translation: 公开了一种用于进行源同步接口的转换测试的方法和装置。 系统包括源同步发射机和源同步接收机。 源同步发射机包括第一可扫描触发器，其具有耦合到源同步接收器中的第二可扫描触发器的数据输入的输出。 在转换测试期间，源同步发射机被配置为将数据从第一可扫描触发器发送到第二可扫描触发器，以及以操作时钟速度的时钟信号。 第一可扫描触发器耦合到被配置为引起发送数据的转换的反馈电路。 第二个可扫描的触发器可以捕获所发送的数据。 捕获的数据可以随后用于确定是否由第二可扫描的翻转器检测到期望的转换。

公开(公告)号：US12216161B2

公开(公告)日：2025-02-04

申请号：US18323946

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Bo Yang ,  Antonietta Oliva ,  Michael R. Seningen ,  Vasu P. Ganti ,  Vijay M. Bettada

IPC: G01R31/00 ,  G01R31/3185

Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.