公开(公告)号：US10147499B1

公开(公告)日：2018-12-04

申请号：US15174192

申请日：2016-06-06

Applicant: Apple Inc.

Inventor： Dragos F. Botea

IPC: G11C29/12 ,  G06F3/06 ,  G11C7/22 ,  G11C29/08

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test to determine whether a portion of a memory is operational at a specified amount of time after a power-up request by performing operations. The operations may include sending a power-up request to the portion. The operations may further include sending, at the specified amount of time after the power-up request, a write request for a write operation at the portion. The operations may further include sending a read request that requests a read operation for data written by the write operation. The operations may further include determining, based on data received in response to the read request, whether the portion correctly performed the read operation and the write operation.

公开(公告)号：US20160093400A1

公开(公告)日：2016-03-31

申请号：US14502458

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Dragos F. Botea

IPC: G11C29/38

CPC classification number: G11C29/38 ,  G11C29/26 ,  G11C2029/2602

Abstract: Techniques are disclosed relating to testing logic in integrated circuits based on power being received by the integrated circuit. In one embodiment, an integrated circuit includes a memory and a self-test unit. The self-test unit is configured to receive an indication that identifies a memory block as being in a low-power state and to determine whether to disregard test data read from the one or more memory banks. In some embodiments, the self-test unit may be configured to mask a portion of test result related to the test data that the self-test unit has determined to disregard. The self-test unit may include an error validation logic configured to determine a validity of test data received from a memory based on a power activation status (e.g., whether the memory is powered on or off) associated with the memory.

Abstract translation: 公开了基于由集成电路接收的功率的集成电路中的测试逻辑的技术。 在一个实施例中，集成电路包括存储器和自检单元。 自检单元被配置为接收将存储器块识别为低功率状态的指示，并且确定是否忽略从一个或多个存储体读取的测试数据。 在一些实施例中，自检单元可以被配置为掩蔽与自检单元已经确定为忽视的测试数据相关的测试结果的一部分。 自检单元可以包括错误验证逻辑，该错误验证逻辑被配置为基于与存储器相关联的功率激活状态（例如，存储器是否通电或断开）来确定从存储器接收的测试数据的有效性。

公开(公告)号：US09607715B1

公开(公告)日：2017-03-28

申请号：US15172768

申请日：2016-06-03

Applicant: Apple Inc.

Inventor： Dragos F. Botea

IPC: G11C7/00 ,  G11C29/08 ,  G11C7/10 ,  G11C29/50

CPC classification number: G11C29/08 ,  G11C29/02 ,  G11C29/50

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing operations. The operations may include causing a first value to be stored at the memory circuit as a current data value. The operations may further include subsequently causing the first value to be sent to the memory circuit as a current comparison data value. The operations may further include causing the internal comparator to compare the current data value to the current comparison data value. The operations may further include receiving a current match value that indicates whether the current data value matches the current comparison data value. In some embodiments, the memory testing circuit may be configured to enable a self-test circuit to detect errors regarding functions of the memory circuit that the self-test circuit is not designed to test.

公开(公告)号：US20160086678A1

公开(公告)日：2016-03-24

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。

公开(公告)号：US20170084349A1

公开(公告)日：2017-03-23

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US09589672B2

公开(公告)日：2017-03-07

申请号：US14502458

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Dragos F. Botea

IPC: G11C29/38 ,  G11C29/26

CPC classification number: G11C29/38 ,  G11C29/26 ,  G11C2029/2602

Abstract: Techniques are disclosed relating to testing logic in integrated circuits based on power being received by the integrated circuit. In one embodiment, an integrated circuit includes a memory and a self-test unit. The self-test unit is configured to receive an indication that identifies a memory block as being in a low-power state and to determine whether to disregard test data read from the one or more memory banks. In some embodiments, the self-test unit may be configured to mask a portion of test result related to the test data that the self-test unit has determined to disregard. The self-test unit may include an error validation logic configured to determine a validity of test data received from a memory based on a power activation status (e.g., whether the memory is powered on or off) associated with the memory.

Abstract translation: 公开了基于由集成电路接收的功率的集成电路中的测试逻辑的技术。 在一个实施例中，集成电路包括存储器和自检单元。 自检单元被配置为接收将存储器块识别为低功率状态的指示，并且确定是否忽略从一个或多个存储体读取的测试数据。 在一些实施例中，自检单元可以被配置为掩蔽与自检单元已经确定为忽视的测试数据相关的测试结果的一部分。 自检单元可以包括错误验证逻辑，该错误验证逻辑被配置为基于与存储器相关联的功率激活状态（例如，存储器是否通电或断开）来确定从存储器接收的测试数据的有效性。

公开(公告)号：US10026499B2

公开(公告)日：2018-07-17

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C7/00 ,  G11C8/00 ,  G11C29/56

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US09514842B2

公开(公告)日：2016-12-06

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/56

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。