公开(公告)号：US10468406B2

公开(公告)日：2019-11-05

申请号：US14509750

申请日：2014-10-08

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/15 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

公开(公告)号：US09552206B2

公开(公告)日：2017-01-24

申请号：US13232774

申请日：2011-09-14

申请人： William M. Johnson ,  Murali S. Chinnakonda ,  Jeffrey L. Nye ,  Toshio Nagata ,  John W. Glotzbach ,  Hamid R. Sheikh ,  Ajay Jayaraj ,  Stephen Busch ,  Shalini Gupta ,  Robert J.P. Nychka ,  David H. Bartley ,  Ganesh Sundararajan

发明人： William M. Johnson ,  Murali S. Chinnakonda ,  Jeffrey L. Nye ,  Toshio Nagata ,  John W. Glotzbach ,  Hamid R. Sheikh ,  Ajay Jayaraj ,  Stephen Busch ,  Shalini Gupta ,  Robert J.P. Nychka ,  David H. Bartley ,  Ganesh Sundararajan

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/30076 ,  G06F8/40 ,  G06F9/30 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/355 ,  G06F9/3552 ,  G06F9/3853 ,  G06F9/3887 ,  G06F9/3891 ,  G06F15/16 ,  G06F15/80 ,  G06F15/8053

摘要： Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

摘要翻译： 传统上，在多核系统中提供并行处理非常困难。 然而，这里提供了一种系统，其中串行源代码被自动转换为并行源代码，并且“即时”重新配置处理集群，以根据存储器和计算资源的分配来容纳并行化代码。 因此，处理集群及其相应的系统编程工具提供可以对从用户透明的串行程序执行并行处理的系统。 通常，连接到主处理器的地址和数据引线的控制节点使用消息来控制处理集群中的数据的处理。 集群包括并行处理器的节点，共享功能存储器，全局加载/存储以及所有通过消息总线连接到控制节点的硬件加速器。 交叉开关数据互连将数据路由到与消息总线分离的集群电路。

公开(公告)号：US09419120B2

公开(公告)日：2016-08-16

申请号：US14533752

申请日：2014-11-05

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

摘要翻译： 提供了一种晶体管器件，其包括基底结构和覆盖在基底结构上的超晶格结构，并且包括具有倾斜侧壁的多通道脊。 多通道脊包括多个异质结构，每个异质结构形成多通道脊的通道，其中至少一个异质结构的参数相对于多个异质结构中的其它异质结构而变化。 晶体管器件还包括三边形栅极接触，其沿着其深度的至少一部分包围并基本上围绕多通道脊的顶部和侧面。

公开(公告)号：US08639050B2

公开(公告)日：2014-01-28

申请号：US13276896

申请日：2011-10-19

申请人： Shalini Gupta ,  Rajesh Narasimha ,  Aziz Umit Batur

发明人： Shalini Gupta ,  Rajesh Narasimha ,  Aziz Umit Batur

IPC分类号： G06K9/40

CPC分类号： G06T5/002 ,  G06T5/007 ,  G06T2207/20004 ,  G06T2207/20012

摘要： Dynamic adjustment of noise filter strengths for use with dynamic range enhancement of images is performed to produce better quality images by adapting dynamically to the image noise profile. Global and local brightness and contrast enhancement (GLBCE) is performed on a digital image to form an enhanced image. The GLBCE applies local gain values to the digital image based on local intensity values. A GLBCE gain versus intensity curve is determined for the enhanced image. A set of noise filter thresholds is adjusted in response to the GLBCE gain versus intensity curve to form a set of dynamically adjusted noise filter thresholds. The enhanced image is noise filtered using the set of dynamically adjusted noise filter thresholds to form a noise filtered enhanced image.

摘要翻译： 执行用于图像的动态范围增强的噪声滤波器强度的动态调整，以通过动态地适应图像噪声分布来产生更好质量的图像。 在数字图像上执行全局和局部亮度和对比度增强（GLBCE）以形成增强图像。 GLBCE根据局部强度值将局部增益值应用于数字图像。 确定增强图像的GLBCE增益对强度曲线。 响应于GLBCE增益对强度曲线来调整一组噪声滤波器阈值以形成一组动态调整的噪声滤波器阈值。 增强图像使用一组动态调整的噪声滤波器阈值进行噪声滤波，以形成噪声滤波增强图像。

公开(公告)号：US07689635B2

公开(公告)日：2010-03-30

申请号：US11260863

申请日：2005-10-27

申请人： Shalini Gupta ,  Sumanta Sarkar

发明人： Shalini Gupta ,  Sumanta Sarkar

IPC分类号： G06F7/00

CPC分类号： G06F5/015 ,  G06F7/762 ,  G06F7/768

摘要： An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or right shift of bits of the digital data word (both logical and arithmetic) and rotation (to the left or right) of bits of the word. The proposed circuit produces the required output in a single cycle.

摘要翻译： 一种使用桶形移位器的区域高效数据移位器/旋转器。 本发明是一种电路，其使用单个桶形移位器并且可控制地实现数字数据字的位的左移或右移或旋转。 该电路是可动态控制的，以实现数字数据字（逻辑和运算）和字的位（左或右）的位的左移或右移。 所提出的电路在单个周期中产生所需的输出。

公开(公告)号：US10084075B2

公开(公告)日：2018-09-25

申请号：US15624445

申请日：2017-06-15

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/15

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US20170288045A1

公开(公告)日：2017-10-05

申请号：US15624445

申请日：2017-06-15

申请人： BETTINA A. NECHAY ,  SHALINI GUPTA ,  MATTHEW RUSSELL KING ,  ERIC J. STEWART ,  ROBERT S. HOWELL ,  JUSTIN ANDREW PARKE ,  HARLAN CARL CRAMER ,  HOWELL GEORGE HENRY ,  RONALD G. FREITAG ,  KAREN MARIE RENALDO

发明人： BETTINA A. NECHAY ,  SHALINI GUPTA ,  MATTHEW RUSSELL KING ,  ERIC J. STEWART ,  ROBERT S. HOWELL ,  JUSTIN ANDREW PARKE ,  HARLAN CARL CRAMER ,  HOWELL GEORGE HENRY ,  RONALD G. FREITAG ,  KAREN MARIE RENALDO

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/15 ,  H01L29/20

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US20060248134A1

公开(公告)日：2006-11-02

申请号：US11260863

申请日：2005-10-27

申请人： Shalini Gupta ,  Sumanta Sarkar

发明人： Shalini Gupta ,  Sumanta Sarkar

IPC分类号： G06F7/00

CPC分类号： G06F5/015 ,  G06F7/762 ,  G06F7/768

摘要： An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or right shift of bits of the digital data word (both logical and arithmetic) and rotation (to the left or right) of bits of the word. The proposed circuit produces the required output in a single cycle.

摘要翻译： 一种使用桶形移位器的区域高效数据移位器/旋转器。 本发明是一种电路，其使用单个桶形移位器并且可控制地实现数字数据字的位的左移或右移或旋转。 该电路是可动态控制的，以实现数字数据字（逻辑和运算）和字的位（左或右）的位的左移或右移。 所提出的电路在单个周期中产生所需的输出。

公开(公告)号：US20060211022A1

公开(公告)日：2006-09-21

申请号：US11361415

申请日：2006-02-23

申请人： Shuqian Jing ,  Francesca Civoli ,  Shalini Gupta ,  Daniel Halperin ,  Jason Pennucci ,  Steven Swanson ,  Yan Yu

发明人： Shuqian Jing ,  Francesca Civoli ,  Shalini Gupta ,  Daniel Halperin ,  Jason Pennucci ,  Steven Swanson ,  Yan Yu

IPC分类号： C12Q1/68 ,  G01N33/53

CPC分类号： G01N33/5008 ,  G01N33/5011 ,  G01N33/5023 ,  G01N33/5308 ,  G01N33/564 ,  G01N33/566 ,  G01N33/6854

摘要： The present invention relates to methods of detecting compounds that affect the activity of a therapeutic substance or composition administered to a subject, and to reagents for use in such methods.

摘要翻译： 本发明涉及检测影响施用于受试者的治疗物质或组合物的活性的化合物的方法以及用于这些方法的试剂。

公开(公告)号：US10985243B2

公开(公告)日：2021-04-20

申请号：US16992244

申请日：2020-08-13

申请人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

发明人： Josephine Bea Chang ,  Eric J. Stewart ,  Ken Alfred Nagamatsu ,  Robert S. Howell ,  Shalini Gupta

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L23/29 ,  H01L23/31 ,  H01L29/15 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/778 ,  H01L29/66

摘要： A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.