Invention Grant
US09552206B2 Integrated circuit with control node circuitry and processing circuitry
有权
具有控制节点电路和处理电路的集成电路
- Patent Title: Integrated circuit with control node circuitry and processing circuitry
- Patent Title (中): 具有控制节点电路和处理电路的集成电路
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Application No.: US13232774Application Date: 2011-09-14
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Publication No.: US09552206B2Publication Date: 2017-01-24
- Inventor: William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
- Applicant: William M. Johnson , Murali S. Chinnakonda , Jeffrey L. Nye , Toshio Nagata , John W. Glotzbach , Hamid R. Sheikh , Ajay Jayaraj , Stephen Busch , Shalini Gupta , Robert J.P. Nychka , David H. Bartley , Ganesh Sundararajan
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Frank D. Cimino
- Main IPC: G06F15/16
- IPC: G06F15/16 ; G06F15/80 ; G06F9/30 ; G06F9/355 ; G06F9/38 ; G06F9/45

Abstract:
Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.
Public/Granted literature
- US20120131309A1 HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM Public/Granted day:2012-05-24
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