公开(公告)号：US09223544B2

公开(公告)日：2015-12-29

申请号：US13606998

申请日：2012-09-07

申请人： Helia Naeimi ,  Ralph Nathan ,  Shih-Lien L. Lu ,  John L. Gustafson

发明人： Helia Naeimi ,  Ralph Nathan ,  Shih-Lien L. Lu ,  John L. Gustafson

IPC分类号： G06F7/483 ,  G06F7/38 ,  G06F7/499

CPC分类号： G06F7/483 ,  G06F7/38 ,  G06F7/49989

摘要： A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value.

摘要翻译： 一种用于在计算机中表示数字的方法，装置和系统，包括将浮点数M存储在计算机存储器中; 当通过使用存储器中的至少两个浮点数来访问时，将浮点数M表示为具有下限和上限A和B的间隔; 然后当在计算中使用存储器中的至少三个浮点数时，将M表示为具有下限和上限A和B的间隔。 使用间隔执行计算，并且当数据被写回存储器时，如果间隔的大小是显着的，即大于第一阈值，则可将其存储为间隔。 如果间隔太大，即大于第二阈值，则可以发出关于作为间隔存储的任何数据的可疑精度的警告。

公开(公告)号：US20160093355A1

公开(公告)日：2016-03-31

申请号：US14499067

申请日：2014-09-26

申请人： Helia NAEIMI ,  Shih-Lien L. LU ,  Shigeki TOMISHIMA

发明人： Helia NAEIMI ,  Shih-Lien L. LU ,  Shigeki TOMISHIMA

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

摘要： In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet.During a normal write operation, the bits to the other state are written. Other aspects are described herein.

摘要翻译： 在一个实施例中，诸如自旋传递转矩（STT）随机存取存储器（RAM）的磁阻随机存取存储器（MRAM）例如具有比特单元的子阵列和与子阵列相邻定位的电磁体。 磁场被引导通过第一子阵列的比特单元的铁磁器件，以帮助将子阵列的比特单元的状态从第一状态改变到第二状态，其中比特单元的铁磁器件从并行和/ 反平行极化与另一个平行和反平行极化。 因此，在从电磁铁的帮助下，子阵列的内容可以容易地预设或者擦除为平行或反平行状态之一。 在正常写入操作期间，写入到另一状态的位。 本文描述了其它方面。

公开(公告)号：US09520192B2

公开(公告)日：2016-12-13

申请号：US14320609

申请日：2014-06-30

申请人： Helia Naeimi ,  Shih-Lien L Lu ,  Charles Augustine

发明人： Helia Naeimi ,  Shih-Lien L Lu ,  Charles Augustine

IPC分类号： G06F12/00 ,  G11C14/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC分类号： G11C14/0036 ,  G06F12/0811 ,  G06F12/0893 ,  G06F2212/283 ,  G11C11/1675 ,  G11C14/0081

摘要： In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

摘要翻译： 在将存储器单元写入第一位状态的存储器件比写入第二位状态需要更长的时间时，选择性地执行写入操作可以分摊写入需要较长时间写入的位状态的性能成本。 写入逻辑从写入缓冲区中取出多个高速缓存行，并在一次写入操作中将所有高速缓存行的所有位设置为第一个位状态。 写逻辑然后分别在每个高速缓存线上执行单独的写操作，以选择性地将每个相应高速缓存行的存储单元写入第二位状态。

公开(公告)号：US08134341B2

公开(公告)日：2012-03-13

申请号：US12435378

申请日：2009-05-04

申请人： Helia Naeimi ,  Qing Ma

发明人： Helia Naeimi ,  Qing Ma

IPC分类号： H02J7/00

CPC分类号： H02K7/1861 ,  H02J7/32 ,  H02K7/1853 ,  H02N2/18 ,  Y02B40/90

摘要： Embodiments of the invention relate to a mobile computing device with ambient energy harvesting capability. Embodiments of the invention, when manually operated by a user, convert the kinetic motion of a part of the user's hand, applied onto a controller of the device, to electrical energy. The energy can be used to power the device, or to charge the battery of the device. Embodiments of the invention include an electrical power storage device disposed in a housing, a display screen attached to the housing to display a plurality of user-interactive interfaces, and a manually operable input controller interactable with the interfaces and being coupled to an energy transformer in the housing to electrically charge the power storage device when operated.

摘要翻译： 本发明的实施例涉及具有环境能量收集能力的移动计算设备。 当用户手动操作时，本发明的实施例将应用于设备的控制器上的用户的一部分手的动态转换为电能。 能量可用于为设备供电，或为设备的电池充电。 本发明的实施例包括设置在壳体中的电力存储装置，附接到壳体以显示多个用户交互界面的显示屏以及与该界面相互作用并且耦合到能量变换器的可手动操作的输入控制器 所述壳体在操作时对所述蓄电装置进行充电。

公开(公告)号：US07242601B2

公开(公告)日：2007-07-10

申请号：US10853907

申请日：2004-05-25

申请人： André Dehon ,  Helia Naeimi

发明人： André Dehon ,  Helia Naeimi

IPC分类号： G11C6/06 ,  G11C7/00

CPC分类号： H03K19/1776 ,  B82Y10/00 ,  G11C5/063 ,  G11C8/10 ,  G11C11/34 ,  G11C11/54 ,  G11C29/025 ,  G11C29/08 ,  G11C29/76 ,  G11C29/816 ,  G11C29/832 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778 ,  Y10S977/963

摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.

摘要翻译： 一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。 在施工期间，地址的纳米级电线随机组装。 在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。 存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。

公开(公告)号：US20070127280A1

公开(公告)日：2007-06-07

申请号：US10853907

申请日：2004-05-25

申请人： Andre DeHon ,  Helia Naeimi

发明人： Andre DeHon ,  Helia Naeimi

IPC分类号： G11C5/06

CPC分类号： H03K19/1776 ,  B82Y10/00 ,  G11C5/063 ,  G11C8/10 ,  G11C11/34 ,  G11C11/54 ,  G11C29/025 ,  G11C29/08 ,  G11C29/76 ,  G11C29/816 ,  G11C29/832 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778 ,  Y10S977/963

摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.

摘要翻译： 一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。 在施工期间，地址的纳米级电线随机组装。 在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。 存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。

公开(公告)号：US20150380088A1

公开(公告)日：2015-12-31

申请号：US14320609

申请日：2014-06-30

申请人： HELIA NAEIMI ,  SHIH-LIEN L. LU ,  CHARLES AUGUSTINE

发明人： HELIA NAEIMI ,  SHIH-LIEN L. LU ,  CHARLES AUGUSTINE

IPC分类号： G11C14/00 ,  G06F12/08

CPC分类号： G11C14/0036 ,  G06F12/0811 ,  G06F12/0893 ,  G06F2212/283 ,  G11C11/1675 ,  G11C14/0081

摘要： In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

摘要翻译： 在将存储器单元写入第一位状态的存储器件比写入第二位状态需要更长的时间时，选择性地执行写入操作可以分摊写入需要较长时间写入的位状态的性能成本。 写入逻辑从写入缓冲区中取出多个高速缓存行，并在一次写入操作中将所有高速缓存行的所有位设置为第一个位状态。 写逻辑然后分别在每个高速缓存线上执行单独的写操作，以选择性地将每个相应高速缓存行的存储单元写入第二位状态。

公开(公告)号：US20140136820A1

公开(公告)日：2014-05-15

申请号：US13676796

申请日：2012-11-14

申请人： Helia Naeimi ,  Ralph Nathan ,  Daniel Sorin ,  Shih-Lien L. Lu

发明人： Helia Naeimi ,  Ralph Nathan ,  Daniel Sorin ,  Shih-Lien L. Lu

IPC分类号： G06F9/30

CPC分类号： G06F11/10 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30101

摘要： A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.

摘要翻译： 公开了一种用于回收浮点单元中的错误位的机制。 本公开的系统包括可通信地耦合到存储器的存储器和处理装置。 在一个实施例中，处理装置包括一个浮点单元（FPU），用于通过向FPU应用对浮点数输入的操作产生一个结果值，并使用该结果值产生一个误差值。 FPU还将结果值写入专用于从FPU的操作存储结果的处理装置的第一寄存器，并将该错误值写入专用于从FPU的操作存储错误的处理装置的第二寄存器。

公开(公告)号：US20120079348A1

公开(公告)日：2012-03-29

申请号：US12890513

申请日：2010-09-24

申请人： Helia Naeimi

发明人： Helia Naeimi

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1004 ,  H03M13/09 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/3776

摘要： A semiconductor chip is described having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between an instruction execution core and a memory controller; and, iii) an interconnect path that resides between a cache and a memory controller. The ECC decoder circuitry has an input register to receive data, CRC values associated with the data and residue information associated with the data.

摘要翻译： 描述了一种半导体芯片，其具有沿着以下任一方式设置的ECC解码器电路：i）位于指令执行核心和高速缓存之间的互连路径; ii）驻留在指令执行核心和存储器控制器之间的互连路径; 以及iii）驻留在高速缓存和存储器控制器之间的互连路径。 ECC解码器电路具有用于接收数据的输入寄存器，与数据相关联的CRC值和与数据相关联的残余信息。

公开(公告)号：US20110154157A1

公开(公告)日：2011-06-23

申请号：US12713623

申请日：2010-02-26

申请人： Helia Naeimi

发明人： Helia Naeimi

IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/19 ,  H03M13/07 ,  G06F12/02

CPC分类号： H03M13/2906 ,  H03M13/07 ,  H03M13/19

摘要： In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于产生数据块的混合纠错码的方法。 可以是残余算术汉明码的混合码包括基于数据块的第一残余码和基于数据块的第一奇偶校验码和汉明矩阵。 然后可以通过处理器的数据路径的至少一部分来传送所产生的代码以及数据块。 描述和要求保护其他实施例。