公开(公告)号：US08872247B2

公开(公告)日：2014-10-28

申请号：US12612546

申请日：2009-11-04

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： H01L27/108 ,  G11C8/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02

CPC分类号： H01L27/10826 ,  G11C8/005 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/785

摘要： Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.

摘要翻译： 具有折叠结构的存储器阵列及其制造方法。 具体地，存储器阵列具有一行中的晶体管的一部分相对于同一行中的其它晶体管往复运动和移位。 在行之间形成的沟槽可以在整个阵列中沿着行的方向形成编织图案。 在晶体管的支腿之间形成的沟槽也可以在整个阵列中沿行的方向形成编织图案。

公开(公告)号：US08737157B2

公开(公告)日：2014-05-27

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/00 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20120063256A1

公开(公告)日：2012-03-15

申请号：US13298104

申请日：2011-11-16

申请人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

发明人： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC分类号： G11C8/08 ,  H01L21/8239

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20110317509A1

公开(公告)日：2011-12-29

申请号：US13100874

申请日：2011-05-04

申请人： TAE KIM ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima

发明人： TAE KIM ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima

IPC分类号： G11C8/08 ,  H01L21/82

CPC分类号： H01L27/0207 ,  G11C8/08 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed.

摘要翻译： 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 每个全局字线驱动器包括第一类型的至少一个晶体管。 公开了其他子系统和方法。

公开(公告)号：US07760582B2

公开(公告)日：2010-07-20

申请号：US12130464

申请日：2008-05-30

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G11C8/00

CPC分类号： G11C8/14

摘要： A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the plurality of wordlines is selectively coupled to a lower resistivity shared interconnection line by way of a selected one of a plurality of switching elements each commonly coupled on one end to the shared interconnection line and individually coupled on an opposing end to the plurality of wordlines. Each of the plurality of switching elements is selectively activated to couple one of the plurality of wordlines to the shared interconnection line when the main wordline signal is selectively coupled to one of the plurality of wordlines.

摘要翻译： 一种用于提高存储器件中字线速度的方法和装置。 字线结构包括用于选择性地分配主字线信号的主字线和选择性地耦合到主字线的多个字线。 多个字线中的每一个通过多个开关元件中的选定的一个选择性地耦合到较低电阻率的共用互连线，每个开关元件在一端共同耦合到共用互连线，并且分别耦合到与多个 字线 当主字线信号选择性地耦合到多个字线之一时，多个开关元件中的每一个选择性地被激活以将多个字线中的一个耦合到共享互连线。

公开(公告)号：US20060198232A1

公开(公告)日：2006-09-07

申请号：US11415726

申请日：2006-05-02

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G11C8/00

CPC分类号： G11C8/14

摘要： A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower resistivity shared interconnection line by way of a selected one of a plurality of switching elements each commonly coupled on one end to the shared interconnection line and individually coupled on an opposing end to the plurality of wordlines. Each of the plurality of switching elements is selectively activated to couple one of the plurality of wordlines to the shared interconnection line when the main wordline signal is selectively coupled to one of the plurality of wordlines.

摘要翻译： 一种用于提高存储器件中字线速度的方法和装置。 字线结构包括用于选择性地分配主字线信号的主字线和选择性地耦合到主字线的多个字线。 每个字线通过多个开关元件中的选定的一个选择性地耦合到较低电阻率的共用互连线，每个开关元件在一端共同地耦合到共享互连线并且分别耦合到多个字线的相对端。 当主字线信号选择性地耦合到多个字线之一时，多个开关元件中的每一个选择性地被激活以将多个字线中的一个耦合到共享互连线。

公开(公告)号：US06812532B2

公开(公告)日：2004-11-02

申请号：US10207173

申请日：2002-07-30

申请人： Tsukasa Ooishi ,  Hiroki Shimano ,  Shigeki Tomishima

发明人： Tsukasa Ooishi ,  Hiroki Shimano ,  Shigeki Tomishima

IPC分类号： H01L2976

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L27/10897 ,  H01L29/66825 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

摘要翻译： 为了提供一种没有激光吹扫的地址编程装置，在半导体衬底上形成第一薄栅氧化膜，在其上形成第一栅极，在其上形成第二厚栅极氧化膜，第二栅电极 形成在其上。 这种器件串联连接到相反极性的MOS晶体管，并且这种装置被交叉连接在一起以形成锁存电路。 要编程的数据及其反转版本被写入编程装置。 根据电源接通时锁存器的重量变化，读取编程信息。

公开(公告)号：US06489796B2

公开(公告)日：2002-12-03

申请号：US09754122

申请日：2001-01-05

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G01R3100

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A boosting portion switches between an N channel MOS transistor with high drivability and a P channel MOS transistor with low drivability for transmitting a high potential at an internal node to an output node. The N and P channel MOS transistors are respectively operated when boosted potential Vpp is low and high.

摘要翻译： 升压部分在具有高驱动性的N沟道MOS晶体管和具有低驱动能力的P沟道MOS晶体管之间切换，用于将内部节点的高电位传输到输出节点。 N和P沟道MOS晶体管分别在升压电位Vpp为低电平时工作。

公开(公告)号：US06333869B1

公开(公告)日：2001-12-25

申请号：US09754121

申请日：2001-01-05

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima

IPC分类号： G11C506

CPC分类号： G11C11/4087 ,  G11C7/06 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4091

摘要： First and second memory cell arrays have their respective sides with first and second center circuit bands adjacent thereto, respectively, and provided therein with their respective address latch circuits, row predecode circuits and row decoders. The first and second memory cell arrays share a sense amplifier band having a side with a center cross circuit band adjacent thereto and provided therein with a column decode circuit and a sense amplifier control circuit controlling activating a sense amplifier. As such the number of signal lines between the second center circuit band and the center cross circuit band can be reduced to alleviate thick density of signal lines. Thus there can be provided a DRAM core with readily changeable memory capacity.

摘要翻译： 第一和第二存储单元阵列分别具有与其相邻的第一和第二中心电路带的相应侧，并且在其中设置有各自的地址锁存电路，行预解码电路和行解码器。 第一和第二存储单元阵列共享具有与其相邻的具有中心交叉电路带的一侧的读出放大器带，并在其中设置有列解码​​电路和控制激活读出放大器的读出放大器控制电路。 因此，可以减少第二中心电路带和中心交叉电缆带之间的信号线的数量，以减轻信号线的厚度。 因此，可以提供具有容易改变的存储容量的DRAM内核。

公开(公告)号：US06331956B1

公开(公告)日：2001-12-18

申请号：US09502332

申请日：2000-02-11

申请人： Tsukasa Ooishi ,  Shigeki Tomishima ,  Hiroki Shimano

发明人： Tsukasa Ooishi ,  Shigeki Tomishima ,  Hiroki Shimano

IPC分类号： G11C702

CPC分类号： G11C29/808 ,  G11C29/842

摘要： A redundant memory cell column region provided corresponding to respective regular memory cell column regions can have data read and written through a sub I/O line pair and a main I/O line pair independent to those of the regular memory cell column region. Also, one redundant memory cell column region can be connected to a corresponding global I/O line pair G-I/O of any of the regular memory cell column regions via a multiplexer to be replaceable of any of two regular memory cell column regions.

摘要翻译： 与相应的常规存储单元列区相对应地提供的冗余存储单元列区域可以通过与常规存储单元列区域独立的子I / O线对和主I / O线对读取和写入数据。 此外，一个冗余存储单元列区域可以经由多路复用器连接到任何常规存储器单元列区域的对应全局I / O线对G-I / O，以可替换两个常规存储器单元列区域中的任一个。