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    Semiconductor component having a space saving edge structure
    5.
    发明授权
    Semiconductor component having a space saving edge structure 有权
    半导体元件具有节省空间的边缘结构

    公开(公告)号：US08080858B2

    公开(公告)日：2011-12-20

    申请号：US11833328

    申请日：2007-08-03

    申请人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler

    发明人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler

    IPC分类号： H01L29/02 ,  H01L29/66 ,  H01L29/06 ,  H01L23/58

    CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A Semiconductor component having a space saving edge structure is disclosed. One embodiment provides a first side, a second side, an inner region, an edge region adjoining the inner region in a lateral direction of the semiconductor body, and a first semiconductor layer extending across the inner region and the edge region and having a basic doping of a first conductivity type. At least one active component zone of a second conductivity type, which is complementary to the first conductivity type, is disposed in the inner region in the first semiconductor layer. An edge structure is disposed in the edge region and includes at least one trench extending from the first side into the semiconductor body. An edge electrode is disposed in the trench, a dielectric layer is disposed in the trench between the edge electrode and the semiconductor body, a first edge zone of the second conductivity type adjoin the trench and are at least partially disposed below the trench.

    摘要翻译： 公开了具有节省空间的边缘结构的半导体部件。 一个实施例提供了第一侧面，第二侧面，内部区域，与半导体主体的横向方向上的内部区域相邻的边缘区域以及跨越内部区域和边缘区域延伸并具有基本掺杂的第一半导体层 的第一导电类型。 与第一导电类型互补的至少一个第二导电类型的活性组分区域设置在第一半导体层的内部区域中。 边缘结构设置在边缘区域中并且包括从第一侧延伸到半导体本体中的至少一个沟槽。 边缘电极设置在沟槽中，电介质层设置在边缘电极和半导体本体之间的沟槽中，第二导电类型的第一边缘区域与沟槽相邻并且至少部分地设置在沟槽下方。

    Memory transistor and memory unit with asymmetrical pocket doping region
    6.
    发明申请
    Memory transistor and memory unit with asymmetrical pocket doping region 有权
    存储晶体管和具有不对称口袋掺杂区域的存储单元

    公开(公告)号：US20070080390A1

    公开(公告)日：2007-04-12

    申请号：US11431265

    申请日：2006-05-10

    申请人： Christian Geissler ,  Franz Schuler ,  Danny Shum

    发明人： Christian Geissler ,  Franz Schuler ,  Danny Shum

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416

    摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

    摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域布置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。