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公开(公告)号：US20220416807A1
公开(公告)日：2022-12-29
申请号：US17358131
申请日：2021-06-25
申请人： Intel Corporation
发明人： Ramon SANCHEZ , Kameran AZADET , Martin CLARA , Daniel GRUBER
摘要： A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.
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2.发明授权公开(公告)号：US08400339B2
公开(公告)日：2013-03-19
申请号：US13075956
申请日：2011-03-30
CPC分类号： H03F3/005 , H03F3/45475 , H03F3/45986 , H03G1/0094
摘要： Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node. The switching configuration has multiple switches that are controllable sequentially to place the gain stage circuit in a sampling state, an approximate output voltage storage state, a level shifting and gain state, and an output state.
摘要翻译： 提供了用于向输入信号施加增益的装置和方法的实施例。 开关电容器增益级电路的实施例包括输入节点，输出节点，运算放大器，相关双采样部分，相关电平转换部分和切换配置。 运算放大器具有第一放大器输入，第二放大器输入和放大器输出。 相关双采样部分包括并联布置并选择性地耦合在输入节点和中心节点之间的多个采样电容器和包括耦合到第一放大器输入的第一端子的偏移存储电容器。 相关电平移位部分包括相关电平移位电容器，其包括耦合到输出节点的第一端子。 开关配置具有可以顺序控制的多个开关，以将增益级电路置于采样状态，近似输出电压存储状态，电平移位和增益状态以及输出状态。
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3.发明授权Logarithmic digital to analog converter having multipliers coupled to reference voltages 失效具有耦合到参考电压的乘法器的对数数模转换器公开(公告)号：US06900751B2
公开(公告)日：2005-05-31
申请号：US10611263
申请日：2003-07-02
申请人： Masami Yakabe
发明人： Masami Yakabe
摘要： An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.
摘要翻译： 模拟乘法器11将基准参考电压“Vref 0”提高到第n个功率，从而产生参考电压“Vref 1”。 模拟乘法器12和13将参考电压“Vref 1”依次升高到第n个功率，从而产生参考电压“Vref 2”和“Vref 3”。 开关组38-41控制参考电压“Vref 0”至“Vref 3”，然后与输入电压“Vin”一起发送到模拟乘法器14。 比较器14顺序地将乘法器14的相乘结果“Vx”与从传感器电路2输出的电压“Vout”进行比较，从而产生数字输出值“Dout”。 模拟乘法器14被适当地设定。
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公开(公告)号：US5631648A
公开(公告)日：1997-05-20
申请号：US353615
申请日：1994-12-12
申请人： Takaaki Yamada , Kazuo Kumano , Kazuhiro Takeda
发明人： Takaaki Yamada , Kazuo Kumano , Kazuhiro Takeda
CPC分类号： H04B1/64
摘要： A signal-processing circuit adapted for signal compression and expansion performed in the transmitter and receiver of mobile communication equipment. The signal-processing circuit comprises a multiplication type D/A converter to which an analog signal is applied, a level detector circuit that detects the level of the analog signal, and an A/D converter. The D/A converter converts the analog input signal into an analog output signal having an amplitude corresponding to digital control data. The A/D converter digitizes the output signal from the level detector circuit and supplies it as said digital control data to the D/A converter. These circuits can be fabricated from CMOS circuits.
摘要翻译： 一种适于在移动通信设备的发射机和接收机中执行的信号压缩和扩展的信号处理电路。 该信号处理电路包括一个乘法型D / A转换器，一个模拟信号被施加到其上，一个电平检测电路检测模拟信号的电平，一个A / D转换器。 D / A转换器将模拟输入信号转换成具有对应于数字控制数据的振幅的模拟输出信号。 A / D转换器对来自电平检测器电路的输出信号进行数字化，并将其作为数字控制数据提供给D / A转换器。 这些电路可以由CMOS电路制造。
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5.发明授权Data storage apparatus with an A/D converter having a reference voltage control based upon a signal before and after discrimination 失效具有A / D转换器的数据存储装置具有基于鉴别前后的信号的基准电压控制
公开(公告)号：US5546245A
公开(公告)日：1996-08-13
申请号：US074297
申请日：1993-06-09
申请人： Naoki Sato
发明人： Naoki Sato
CPC分类号： H03M1/182 , G11B20/10009 , G11B5/035 , G11B5/09
摘要： A data storage apparatus and method that allows the signal processing circuit to be in integrated form, so that the magnetic storage system may be reduced in size with increased performance is described. The apparatus includes a reproducing head that reproduces information stored on a recording medium, a preamplifier that amplifies the output of the reproducing head, and a low-pass filter. An A/D converter converts the output for the low-pass filter to a digital signal and has a reference voltage. A discriminator is coupled to an output of the A/D converter and discriminates the digital signal. A circuit, coupled to the discriminator, provides negative feedback control of the reference voltage of the A/D converter as a function of the digital signal before the discrimination by the discriminator and the digital signal that has been discriminated by the discriminator.
摘要翻译： 一种允许信号处理电路集成的数据存储装置和方法，从而可以以增加的性能来减小磁存储系统的尺寸。 该装置包括再现记录介质上存储的信息的再现头，放大再现头的输出的前置放大器和低通滤波器。 A / D转换器将低通滤波器的输出转换为数字信号，并具有参考电压。 鉴别器耦合到A / D转换器的输出端并鉴别数字信号。 耦合到鉴别器的电路在鉴别器鉴别之前的数字信号和已被鉴别器识别的数字信号之间提供对A / D转换器参考电压的负反馈控制。
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公开(公告)号：US07348908B2
公开(公告)日：2008-03-25
申请号：US11258030
申请日：2005-10-26
申请人： Keith R. Slavin
发明人： Keith R. Slavin
IPC分类号： H03M1/88
CPC分类号： H03M1/0626 , H03M1/12
摘要： A linearity corrector is provided that reduces distortion in a signal processing system, such as an ADC. The linearity corrector provides a first order signal path having distortion components connected to an adder, and a filter product circuit that is also connected to the adder. A method is provided for reducing distortion by calculating a filter product and adding the filter product to a first order signal having a relative delay such that the filter product reduces, or eliminates, the order of distortions corresponding to the order of the filter product.
摘要翻译： 提供了一种线性校正器，其减少诸如ADC的信号处理系统中的失真。 线性校正器提供具有连接到加法器的失真分量的一阶信号路径，以及也连接到加法器的滤波器乘积电路。 提供了一种通过计算滤波器产品来减少失真的方法，并且将滤波器产品加到具有相对延迟的一阶信号中，使得滤波器产品减少或消除了与滤波器产品的顺序相对应的失真次序。
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7.发明授权Analog multiplexer and variable gain amplifier for intermediate frequency applications 有权用于中频应用的模拟多路复用器和可变增益放大器公开(公告)号：US07106232B2
公开(公告)日：2006-09-12
申请号：US10114576
申请日：2002-04-02
IPC分类号： H03M1/88
CPC分类号： H04B7/082 , H03G1/0088 , H03G3/3052
摘要： A diversity receiver circuit system (10) including a primary channel (20) and a diversity channel (22), where analog input signals are converted to differential signals in both channels (20, 22). The receiver circuit system (10) includes a multiplexer (14) and a variable gain amplifier (12) formed on a single RF integrated circuit chip (16), where the multiplexer (14) is positioned before the amplifier (12). The differential signals in the primary channel (20) and the diversity channel (22) are applied to an amplified path (72, 78) and a non-amplified path (76, 82) in the multiplexer (14). A control signal selects one of the amplified primary channel signal, the non-amplified primary channel signal, the amplified diversity channel signal or the non-amplified diversity channel signal. The selected signal is then applied to a first amplifier stage (88) and a second amplifier stage (96) in the variable gain amplifier (12), where both amplifier stages (88, 96) include an amplified path (90, 98) and a non-amplified path (92, 100).
摘要翻译： 一种包括主要信道（20）和分集信道（22）的分集接收机电路系统（10），其中模拟输入信号被转换成两个信道（20,22）中的差分信号。 接收器电路系统（10）包括形成在单个RF集成电路芯片（16）上的多路复用器（14）和可变增益放大器（12），其中多路复用器（14）位于放大器（12）之前。 主信道（20）和分集信道（22）中的差分信号被施加到多路复用器（14）中的放大路径（72,78）和非放大路径（76,82）。 控制信号选择放大的主信道信号，非放大的主信道信号，放大的分集信道信号或非放大的分集信道信号之一。 所选择的信号然后被施加到可变增益放大器（12）中的第一放大器级（88）和第二放大级（96），其中两个放大级（88,96）包括放大路径（90,98）和 非放大路径（92,100）。
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公开(公告)号：US06972701B2
公开(公告)日：2005-12-06
申请号：US10950271
申请日：2004-09-24
申请人： Christer Jansson
发明人： Christer Jansson
CPC分类号： H03M1/1019 , H03M1/361 , H03M1/70
摘要： A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.
摘要翻译： 包括具有相关联的校准D / A转换器的一组比较器的A / D转换器结构中的AD / A转换器范围校准系统包括用于确定整个比较器组的偏移误差范围的装置（RCC）和装置（R-DAC） 用于将每个校准D / A转换器的动态范围调整到该偏移误差范围。
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9.发明授权
公开(公告)号：US6166671A
公开(公告)日：2000-12-26
申请号：US160541
申请日：1998-09-25
CPC分类号： H03M1/0624 , H03M1/12
摘要： The analog-to-digital converting circuit apparatus of the invention is intended to realize both low voltage operation and high speed operation of an analog-to-digital converting circuit without impairing the precision characteristic. In plural boosting circuits, voltages higher than each supply voltage are generated. These plural boosting circuits are controlled as the control timing is sequentially shifted by the controller. The boosted voltages delivered from the plural boosting circuits are accumulated in the capacitor, and supplied into the analog-to-digital converter. In the analog-to-digital converter, at the timing other than the changeover timing of the converting action of the analog-to-digital converter, the plural boosting circuits are changed over sequentially, and the boosted voltages are converted from analog to digital values.
摘要翻译： 本发明的模拟 - 数字转换电路装置旨在实现模数转换电路的低电压操作和高速操作，而不损害精度特性。 在多个升压电路中，产生高于每个电源电压的电压。 当控制器依次移动控制定时时，控制这些多个升压电路。 从多个升压电路输出的升压电压累积在电容器中，并被提供给模数转换器。 在模数转换器中，在模数转换器的转换动作的转换定时之外的定时，多个升压电路依次改变，升压后的电压从模数转换为数字值 。
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10.发明授权Analog to digital conversion architecture and method with input and reference voltage scaling 有权具有输入和参考电压缩放的模数转换结构和方法公开(公告)号：US08823566B2
公开(公告)日：2014-09-02
申请号：US13537308
申请日：2012-06-29
IPC分类号： H03M1/88
摘要： An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.
摘要翻译： 模数转换器级包括：比较器和逻辑电路，具有不同于上残留电压跳变点和下残余电压跳变点的第一上和下非放大电压跳变点; 和开关电容电路。 比较器和逻辑电路在初始残余计算周期之前配置，以将未缩放输入电压的幅度与第一上限和下限未缩放电压跳变点进行比较，以产生初始输出位，并产生电压缩放和增益控制 信号。 开关电容器电路被配置为对未缩放的输入电压进行采样以接收参考电压，并且接收电压调节和增益控制信号，以选择性地控制开关电容器电路的开关的子集，以缩放未缩放的输入电压样本和参考 并且在初始残留计算周期的单次操作期间产生初始残留电压。
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