公开(公告)号：US20250072214A1

公开(公告)日：2025-02-27

申请号：US18633188

申请日：2024-04-11

Applicant: Sony Group Corporation

Inventor： Hitoshi Tsuno

IPC: H10K59/121 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/66 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L29/788 ,  H10K59/12 ,  H10K59/131

Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

公开(公告)号：US12223994B2

公开(公告)日：2025-02-11

申请号：US18606333

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  H10B51/30 ,  H10B53/30

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

公开(公告)号：US12200926B2

公开(公告)日：2025-01-14

申请号：US17949962

申请日：2022-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

公开(公告)号：US20250017004A1

公开(公告)日：2025-01-09

申请号：US18347542

申请日：2023-07-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN-YAO KO ,  LIANG-TAI KUO ,  SHIH-HSIEN CHEN ,  YINGKIT FELIX TSUI

IPC: H10B41/10 ,  H01L29/423 ,  H01L29/788 ,  H10B41/70

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.

公开(公告)号：US20250014646A1

公开(公告)日：2025-01-09

申请号：US18892390

申请日：2024-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-bo SHIM ,  Ji-ho CHO ,  Yong-seok KIM ,  Byoung-taek KIM ,  Sun-gyung HWANG

IPC: G11C16/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L29/788 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

公开(公告)号：US12193226B2

公开(公告)日：2025-01-07

申请号：US18344957

申请日：2023-06-30

Applicant: Kioxia Corporation

Inventor： Keiichi Sawa

IPC: H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

公开(公告)号：US12185544B2

公开(公告)日：2024-12-31

申请号：US17867501

申请日：2022-07-18

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H10B41/27

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12185532B2

公开(公告)日：2024-12-31

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

公开(公告)号：US20240379879A1

公开(公告)日：2024-11-14

申请号：US18612961

申请日：2024-03-21

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Caiyun CHEN ,  Zhen GU ,  Lei ZHANG ,  Chao CHEN ,  Haoyu CHEN

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: The present application discloses a super flash, wherein a device cell includes a first gate trench at the top of a source region, a first spacer structure is formed on a side surface of the first gate trench in a self-aligned manner, and the first spacer structure is formed by means of self-aligned etch of a stack layer of a first tunneling dielectric layer, a floating gate, and a second oxide layer. The material of the floating gate comprises a TiN layer. A second spacer structure is formed on a second side surface of the first spacer structure in a self-aligned manner, and the second spacer structure is formed by means of self-aligned etch of a stack layer of a third silicon nitride layer, a fourth oxide layer, and a fifth silicon nitride layer. The present application further discloses a method for manufacturing a super flash.

公开(公告)号：US12144173B2

公开(公告)日：2024-11-12

申请号：US18328080

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Bo Shu ,  Chung-Jen Huang ,  Yun-Chi Wu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/06 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B20/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/49 ,  H10B43/30 ,  H10B43/40 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/51

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.