公开(公告)号：US20170194342A1

公开(公告)日：2017-07-06

申请号：US14987452

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAU-YAN LU ,  SHIH-HSIEN CHEN ,  CHUN-YAO KO ,  FELIX YING-KIT TSUI

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11521

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.

公开(公告)号：US20250017004A1

公开(公告)日：2025-01-09

申请号：US18347542

申请日：2023-07-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHUN-YAO KO ,  LIANG-TAI KUO ,  SHIH-HSIEN CHEN ,  YINGKIT FELIX TSUI

IPC: H10B41/10 ,  H01L29/423 ,  H01L29/788 ,  H10B41/70

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.

公开(公告)号：US20170125425A1

公开(公告)日：2017-05-04

申请号：US14928688

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHIH-HSIEN CHEN ,  HAU-YAN LU ,  LIANG-TAI KUO ,  CHUN-YAO KO ,  FELIX YING-KIT TSUI

IPC: H01L27/115

CPC classification number: H01L27/1156 ,  G11C16/0433 ,  G11C2216/04 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.