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17317 条记录 (耗时 0.045 秒)

    Impedance calibration circuit, impedance calibration method, and memory
    2.
    发明授权
    Impedance calibration circuit, impedance calibration method, and memory 有权

    公开(公告)号：US12132479B2

    公开(公告)日：2024-10-29

    申请号：US17952850

    申请日：2022-09-26

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Zhiqiang Zhang

    IPC分类号： H03K19/00 ,  G11C7/10

    CPC分类号： H03K19/0005 ,  G11C7/1048

    摘要： An impedance calibration circuit, an impedance calibration method, and a memory are provided. The impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module. The parameter module is configured to perform environment detection processing and output an environment parameter signal; the initial value generation module is configured to receive the environment parameter signal, and output an initial calibration value based on the environment parameter signal when the calibration instruction signal is received; and the calibration module is configured to receive the initial calibration value, and perform impedance calibration processing based on the initial calibration value when the calibration instruction signal is received.

    Non-volatile memory device for detecting defects of bit lines and word lines
    3.
    发明授权
    Non-volatile memory device for detecting defects of bit lines and word lines 有权

    公开(公告)号：US12131798B2

    公开(公告)日：2024-10-29

    申请号：US17972300

    申请日：2022-10-24

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

    IPC分类号： G11C7/10 ,  G06F11/10

    CPC分类号： G11C7/1057 ,  G06F11/1076

    摘要： Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

    VARIABLE PAGE SIZE ARCHITECTURE
    8.
    发明公开
    VARIABLE PAGE SIZE ARCHITECTURE 审中-公开

    公开(公告)号：US20240347088A1

    公开(公告)日：2024-10-17

    申请号：US18617019

    申请日：2024-03-26

    申请人： Micron Technology, Inc.

    发明人： Corrado Villa

    IPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/10 ,  G11C8/10 ,  G11C29/18

    CPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/10 ,  G11C2029/1804 ,  G11C2207/2245

    摘要： Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

    Circuit for receiving data, system for receiving data, and memory device
    9.
    发明授权
    Circuit for receiving data, system for receiving data, and memory device 有权

    公开(公告)号：US12119077B2

    公开(公告)日：2024-10-15

    申请号：US17934695

    申请日：2022-09-23

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Feng Lin

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/067 ,  G11C7/1063 ,  G11C7/222

    摘要： Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.

    ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM
    10.
    发明公开
    ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240339136A1

    公开(公告)日：2024-10-10

    申请号：US18206488

    申请日：2023-06-06

    申请人： Silicon Storage Technology, Inc.

    发明人： Kha Nguyen ,  Anh Ly ,  Hieu Van Tran ,  Hien Pham ,  Henry Tran

    IPC分类号： G11C7/10 ,  G11C7/12

    CPC分类号： G11C7/1039 ,  G11C7/12

    摘要： Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.