公开(公告)号：US20230144141A1

公开(公告)日：2023-05-11

申请号：US17972300

申请日：2022-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

IPC: G11C7/10 ,  G06F11/10

CPC classification number: G11C7/1057 ,  G06F11/1076

Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

公开(公告)号：US12131798B2

公开(公告)日：2024-10-29

申请号：US17972300

申请日：2022-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

IPC: G11C7/10 ,  G06F11/10

CPC classification number: G11C7/1057 ,  G06F11/1076

Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.