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公开(公告)号：US12046273B2
公开(公告)日：2024-07-23
申请号：US17936166
申请日：2022-09-28
发明人： Akira Yamashita , Kenji Asaki
IPC分类号： G11C11/4093 , G01R31/26 , G11C7/10 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4093 , G11C11/4076 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.
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公开(公告)号：US20200051603A1
公开(公告)日：2020-02-13
申请号：US16058687
申请日：2018-08-08
摘要： Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
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公开(公告)号：US20190304532A1
公开(公告)日：2019-10-03
申请号：US16444365
申请日：2019-06-18
IPC分类号： G11C11/4076 , H03K5/135 , H03K3/037 , H03K5/1534 , H03K5/05
摘要： Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
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公开(公告)号：US20190272865A1
公开(公告)日：2019-09-05
申请号：US16420036
申请日：2019-05-22
发明人： Akira Yamashita
IPC分类号： G11C11/4074 , G11C11/4093 , G11C11/4094 , G11C11/408 , G11C11/4076 , G11C11/4072 , G11C7/10 , G11C7/02
摘要： Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.
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公开(公告)号：US10937473B2
公开(公告)日：2021-03-02
申请号：US16058687
申请日：2018-08-08
摘要： Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
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公开(公告)号：US10803923B2
公开(公告)日：2020-10-13
申请号：US16444365
申请日：2019-06-18
IPC分类号： G11C11/4076 , H03K5/1534 , H03K5/05 , H03K3/037 , H03K5/135 , G11C7/22 , H03K5/15 , H03K5/00
摘要： Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
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公开(公告)号：US10418081B1
公开(公告)日：2019-09-17
申请号：US16156862
申请日：2018-10-10
IPC分类号： G11C7/22 , G11C11/4076 , H03K5/15 , H03K5/00
摘要： Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
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公开(公告)号：US20190043550A1
公开(公告)日：2019-02-07
申请号：US15669392
申请日：2017-08-04
发明人： Akira Yamashita
IPC分类号： G11C11/4074 , G11C11/4072 , G11C11/4076 , G11C11/408 , G11C11/4093 , G11C11/4094
CPC分类号： G11C11/4074 , G11C7/02 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/1093 , G11C11/4072 , G11C11/4076 , G11C11/4085 , G11C11/4093 , G11C11/4094
摘要： Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.
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9.发明申请公开(公告)号：US20200118608A1
公开(公告)日：2020-04-16
申请号：US16436655
申请日：2019-06-10
IPC分类号： G11C7/22 , H03K5/15 , G11C11/4076
摘要： Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
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公开(公告)号：US10339998B1
公开(公告)日：2019-07-02
申请号：US15937552
申请日：2018-03-27
IPC分类号： G11C11/4076 , H03K5/1534 , H03K5/05 , H03K3/037 , H03K5/135 , H03K5/00
摘要： Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
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