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公开(公告)号：US11901036B2
公开(公告)日：2024-02-13
申请号：US17692066
申请日：2022-03-10
发明人： Katsuhiro Kitagawa
摘要： Apparatuses for controlling power supply to sense amplifiers are described. An example apparatus includes a bank. The bank includes: a first plurality of memory cells; a second plurality of memory cells; first sense amplifiers coupled to the first plurality of memory cells; second sense amplifiers coupled to the second plurality of memory cells; a first power control circuit and a coupled to the first sense amplifiers at a common power supply node; and a second power control circuit coupled to the second sense amplifiers at the common power supply node. The first and second power control circuits receive a plurality of control signals. The first and second power control circuits comprise first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals. The first drive strength and the second drive strength are different from each other.
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公开(公告)号：US11651815B2
公开(公告)日：2023-05-16
申请号：US17590710
申请日：2022-02-01
IPC分类号： G11C11/408 , G11C11/406
CPC分类号： G11C11/4087 , G11C11/40615
摘要： Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
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公开(公告)号：US20150002201A1
公开(公告)日：2015-01-01
申请号：US14318067
申请日：2014-06-27
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.
摘要翻译： 本文公开了一种装置，包括：占空比校正电路，其基于占空比控制信号调整第一时钟信号的占空比，以产生第二时钟信号; 延迟线延迟所述第二时钟信号以产生第三时钟信号; 以及占空比检测器检测第二时钟信号的占空比以在第一模式中产生占空比控制信号，并且检测第三时钟信号的占空比以在第二模式中产生占空比控制信号。
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公开(公告)号：US11270758B2
公开(公告)日：2022-03-08
申请号：US16942503
申请日：2020-07-29
IPC分类号： G11C7/00 , G11C11/408 , G11C11/406
摘要： Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
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公开(公告)号：US20200051603A1
公开(公告)日：2020-02-13
申请号：US16058687
申请日：2018-08-08
摘要： Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
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公开(公告)号：US20190304532A1
公开(公告)日：2019-10-03
申请号：US16444365
申请日：2019-06-18
IPC分类号： G11C11/4076 , H03K5/135 , H03K3/037 , H03K5/1534 , H03K5/05
摘要： Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
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公开(公告)号：US20170093386A1
公开(公告)日：2017-03-30
申请号：US14866250
申请日：2015-09-25
发明人： Katsuhiro Kitagawa
IPC分类号： H03K5/156
CPC分类号： H03K5/1565 , H03K5/159
摘要： Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.
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公开(公告)号：US20150002196A1
公开(公告)日：2015-01-01
申请号：US14317893
申请日：2014-06-27
IPC分类号： H03L7/197
CPC分类号： H03L7/1972 , H03L7/0814
摘要： Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase determination circuit comparing a phase of the first clock signal with a phase of the second clock signal to generate a phase determination signal, an up-down counter updating the count value according to the phase determination signal each time an update signal is activated, and an update control circuit generating the update signal at a variable interval.
摘要翻译： 本文公开了一种装置，包括：第一延迟电路，根据计数值延迟第一时钟信号以产生第二时钟信号;相位确定电路，将第一时钟信号的相位与第二时钟信号的相位进行比较，以产生 相位确定信号，每当激活更新信号时根据相位确定信号更新计数值的升降计数器，以及以可变间隔产生更新信号的更新控制电路。
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公开(公告)号：US11605421B2
公开(公告)日：2023-03-14
申请号：US16932567
申请日：2020-07-17
IPC分类号： G11C7/12 , G11C11/4091 , G11C11/4096 , G11C11/4074 , G11C11/4076 , G11C7/06 , G11C7/10 , G11C8/08
摘要： Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.
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公开(公告)号：US20220180914A1
公开(公告)日：2022-06-09
申请号：US17114338
申请日：2020-12-07
发明人： Katsuhiro Kitagawa
IPC分类号： G11C11/4074 , G11C11/406 , G11C11/4096
摘要： Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.
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