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11 条记录 (耗时 0.016 秒)

    Photodiode
    2.
    发明授权
    Photodiode 有权
    光电二极管

    公开(公告)号：US07341921B2

    公开(公告)日：2008-03-11

    申请号：US10556460

    申请日：2004-05-14

    申请人： John Carlton Jackson ,  John Alderman ,  Alan Mathewson

    发明人： John Carlton Jackson ,  John Alderman ,  Alan Mathewson

    IPC分类号： H01L21/20 ,  H01L31/72 ,  H01L31/328

    CPC分类号： H01L31/107

    摘要： The invention provides a method of manufacturing an avalanche diode comprising the steps of applying a mask (6) over an active diode region (5) in a wafer (1), and damaging the region the surrounding the active diode region by breaking bonds in the semiconductor lattice to provide gettering sites in this surrounding region.

    摘要翻译： 本发明提供一种制造雪崩二极管的方法，包括以下步骤：在晶片（1）上的有源二极管区域（5）上施加掩模（6），并且通过断开所述有源二极管区域 半导体晶格，以在这个周边地区提供吸气点。

    Thermoelectric module with Si/SiGe and B4C/B9C super-lattice legs
    3.
    发明授权
    Thermoelectric module with Si/SiGe and B4C/B9C super-lattice legs 失效
    具有Si / SiGe和B4C / B9C超晶格腿的热电模块

    公开(公告)号：US07038234B2

    公开(公告)日：2006-05-02

    申请号：US10818028

    申请日：2004-04-05

    申请人： Saeid Ghamaty ,  Norbert B. Elsner ,  John C. Bass

    发明人： Saeid Ghamaty ,  Norbert B. Elsner ,  John C. Bass

    IPC分类号： H01L29/09 ,  H01L31/328 ,  H01L31/336 ,  H01L31/72 ,  H01L31/109

    CPC分类号： H01L35/22 ,  H01L29/155 ,  H01L35/26 ,  H01L35/32 ,  H01L35/34 ,  Y10S257/93

    摘要： A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.76 cm designed to produce 70 Watts with a temperature difference of 300 degrees C with a module efficiency of about 30 percent.

    摘要翻译： 超晶格热电器件。 该装置包括p腿和n腿，每个腿具有大量具有不同电子带隙的两种材料的交替层。 器件中的n脚由硅和硅锗的交替层组成。 P腿包括B 4 C和B 9 C的交替层。 在优选的实施方案中，这些层是约100埃厚。 申请人已经制造和测试了第一Si / SiGe（n-leg）和B 4 C / B 9 C（p-leg）量子阱热电偶。 在5微米Si衬底上，每条腿仅为11微米厚。 然而，在实际测试中，热电偶以250摄氏度的T 达到惊人的14％的效率运行。根据本发明制造的热电模块可用于两个冷却应用以及电力 代。 该优选实施例是大约6cm×6cm×0.76cm的热电10×10蛋箱型模块，设计成产生70瓦，温度差为300摄氏度，模块效率约为30％。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07091528B2

    公开(公告)日：2006-08-15

    申请号：US10902120

    申请日：2004-07-30

    申请人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama

    发明人： Masanobu Nogome ,  Akiyoshi Tamura ,  Keiichi Murayama

    IPC分类号： H01L31/328

    CPC分类号： H01L29/7371 ,  H01L29/0821

    摘要： A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

    摘要翻译： 提供了一种在高功率输出上具有改进的击穿电压的半导体器件，该半导体器件包括n型GaAs子集电极层，形成在集电极层和子集电极层之间的n型GaAs中间集电极层，n型GaAs 集电极层，p型GaAs基极层，n型InGaP第二发射极层，n型GaAs第一发射极层和n型InGaAs发射极接触层，中间集电极层中的杂质浓度为 高于集电体层中的杂质浓度，并且低于子集电极层中的杂质浓度。

    Semiconductor optical devices and optical modules
    5.
    发明授权
    Semiconductor optical devices and optical modules 有权
    半导体光学器件和光学模块

    公开(公告)号：US07038233B2

    公开(公告)日：2006-05-02

    申请号：US10782897

    申请日：2004-02-23

    申请人： Tomonobu Tsuchiya ,  Tsukuru Ohtoshi

    发明人： Tomonobu Tsuchiya ,  Tsukuru Ohtoshi

    IPC分类号： H01L29/06 ,  H01L31/328 ,  H01L31/336 ,  H01L31/72 ,  H01L31/109

    CPC分类号： B82Y20/00 ,  H01S5/02208 ,  H01S5/02284 ,  H01S5/0683 ,  H01S5/2224 ,  H01S5/2275 ,  H01S5/3403 ,  H01S5/34306 ,  H01S5/34313 ,  H01S5/34366

    摘要： An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.

    摘要翻译： 预期基于InGaAlAs的掩埋式激光器可以改善器件的性能，但是由于在有源层中包含Al，所以在再生长界面处产生缺陷，难以实现光通信所需的长期可靠性。 提供了一种半导体光学器件和包括安装在封装衬底上的封装衬底和半导体光学器件的光学模块，由此通过使用Al组成比降低来实现器件性能和长期可靠性的提高 拉伸应变量子阱层。

    Semiconductor component
    6.
    发明授权
    Semiconductor component 有权
    半导体元件

    公开(公告)号：US06933546B2

    公开(公告)日：2005-08-23

    申请号：US10391040

    申请日：2003-03-17

    申请人： Vishnu Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose ,  Todd C. Roggenbauer

    发明人： Vishnu Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose ,  Todd C. Roggenbauer

    IPC分类号： H01L27/02 ,  H01L27/08 ,  H01L29/866 ,  H01L31/0328 ,  H01L31/328

    CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L27/0814 ,  Y10S438/983

    摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

    摘要翻译： 半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320） ，340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域 半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。 在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。 在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

    Solid state heterojunction and solid state sensitized photovoltaic cell
    8.
    发明授权
    Solid state heterojunction and solid state sensitized photovoltaic cell 有权
    固态异质结和固态光敏电池

    公开(公告)号：US07042029B2

    公开(公告)日：2006-05-09

    申请号：US10885224

    申请日：2004-07-06

    申请人： Michael Graetzel ,  Robert Plass ,  Udo Bach

    发明人： Michael Graetzel ,  Robert Plass ,  Udo Bach

    IPC分类号： H01L31/328 ,  H01L31/06

    CPC分类号： H01L51/4226 ,  B82Y10/00 ,  H01L51/0059 ,  H01L51/4213 ,  H01L51/426 ,  Y02E10/549

    摘要： A solid state p-n heterojunction comprising an electron conductor and a hole conductor; it further comprises a sensitising semiconductor, said sensitizing semiconductor being located at an interface between said electron conductor and said hole conductor. In particular, the sensitizing semiconductor is in form of quantum-dots. A solid state sensitized photovoltaic cell comprises such a heterojunction between two electrodes.

    摘要翻译： 包含电子导体和空穴导体的固态p-n异质结; 它还包括敏化半导体，所述敏化半导体位于所述电子导体和所述孔导体之间的界面处。 特别地，敏化半导体是量子点的形式。 固态敏化光伏电池包括两个电极之间的这种异质结。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    9.
    发明授权
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号：US06987310B2

    公开(公告)日：2006-01-17

    申请号：US10851336

    申请日：2004-05-24

    申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

    IPC分类号： H01L31/328 ,  H01L31/72 ,  H01L31/336 ,  H01L31/109 ,  H01L39/60

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

    摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。