公开(公告)号：US06770906B2

公开(公告)日：2004-08-03

申请号：US10368964

申请日：2003-02-19

Applicant: Tim J. Corbett ,  Raymond P. Scholer ,  Fernando Gonzalez

Inventor： Tim J. Corbett ,  Raymond P. Scholer ,  Fernando Gonzalez

IPC: H01L2350

CPC classification number: G01R31/2856 ,  G01R31/3163 ,  H01L22/34 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract translation: 一种包括多个测试功能的半导体测试芯片。 半导体测试芯片的测试功能包括焊盘间距和尺寸对芯片设计的影响，关于在接合焊盘上放置引线键合的引线键合布置精度，评估焊盘损坏（凹坑）对芯片面积的影响 在焊接接合焊盘时的接合焊盘，关于使用更薄的锯切切割从晶片切割单个芯片的街道宽度效应，用于热测试能力的热阻抗效应，离子迁移率评估能力以及翻转中的芯片 芯片应用测试能力。

公开(公告)号：US06518649B1

公开(公告)日：2003-02-11

申请号：US09714213

申请日：2000-11-17

Applicant: Tomohiko Iwane ,  Kenji Toyosawa

Inventor： Tomohiko Iwane ,  Kenji Toyosawa

IPC: H01L2350

CPC classification number: H01L24/32 ,  H01L23/4985 ,  H01L23/49866 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/244 ,  H05K3/328 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: The interconnect pattern of the tape carrier in a COF is gold plated other than the part covered by solder resists. The inner leads of the tape carrier and the corresponding gold bumps of electrodes of the semiconductor chip are thermally compressed so that the inner leads penetrate into the gold bumps, thus creating gold-gold compression bonding.

Abstract translation: COF中的带载体的互连图案是除被阻焊剂覆盖的部分之外的镀金。 带状物的内引线和对应的半导体芯片的电极的金凸块被热压缩，使得内引线穿入金凸块，从而产生金 - 金压接。

公开(公告)号：US06300679B1

公开(公告)日：2001-10-09

申请号：US09087674

申请日：1998-06-01

Applicant: Prosanto K. Mukerji ,  Ronald E. Thomas ,  George W. Hawkins ,  Rajesh Srinivasan ,  Colin B. Bosch ,  James H. Knapp ,  Laura J. Norton ,  Michael J. Seddon

Inventor： Prosanto K. Mukerji ,  Ronald E. Thomas ,  George W. Hawkins ,  Rajesh Srinivasan ,  Colin B. Bosch ,  James H. Knapp ,  Laura J. Norton ,  Michael J. Seddon

IPC: H01L2350

CPC classification number: H01L23/4985 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/189

Abstract: A semiconductor component includes a semiconductor chip (341, 502, 601, 701, 1101, 1410, 1501) having first and second surfaces opposite each other, a semiconductor device (301) in the semiconductor chip (341, 502, 601, 701, 1101, 1410, 1501), and a flexible substrate (120, 401, 510, 610, 710, 1000, 1050, 1300, 1401, 1510, 1520) packaging the semiconductor chip (341, 502, 601, 701, 1101, 1410, 1501).

Abstract translation: 半导体元件包括具有彼此相对的第一和第二表面的半导体芯片（341,502,601,701,1101,1410,1501），半导体芯片（341,502,601,701， 1101,1410,1501）以及将半导体芯片（341,502,601,701,1101,1410）封装的柔性基板（120,401,510,610,710,110,1050,1300,1401,1510,1520） ，1501）。

公开(公告)号：US06181009B2

公开(公告)日：2001-01-30

申请号：US09249089

申请日：1999-02-12

Applicant: Yoshiharu Takahashi ,  Toshiaki Shinohara

Inventor： Yoshiharu Takahashi ,  Toshiaki Shinohara

IPC: H01L2350

CPC classification number: H01L23/4951 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/05554 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83894 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic component includes an insulating coating that is electrically conductive when heated disposed on a portion of a surface of a semiconductor chip; electrodes disposed on the surface of the semiconductor chip elsewhere; and inner leads extending from a lead frame and anodically bonded to the insulating coating so that the inner leads are electrically coupled to the electrodes.

Abstract translation: 电子部件包括绝缘涂层，其在被加热时设置在半导体芯片的表面的一部分上是导电的; 设置在其他地方的半导体芯片的表面上的电极; 以及从引线框架延伸并阳极结合到绝缘涂层的内部引线，使得内部引线电耦合到电极。

公开(公告)号：US06703713B1

公开(公告)日：2004-03-09

申请号：US10309478

申请日：2002-12-04

Applicant: Wei-Cheng Tseng ,  Chin Te Chen

Inventor： Wei-Cheng Tseng ,  Chin Te Chen

IPC: H01L2350

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/4824 ,  H01L2224/48475 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/85051 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A window-type multi-chip semiconductor package is provided. A first chip and a second chip are mounted on a surface of a substrate formed with an opening, and a third chip is stacked on the first and second chips, wherein a plurality of bonding wires formed through the opening are used to electrically interconnect the chips and electrically connect the chips to the substrate. The chips are encapsulated by a first encapsulant formed on the surface of the substrate, and a second encapsulant is formed on an opposing surface of the substrate for encapsulating the bonding wires. With the chips being mounted on the same surface of the substrate, conductive elements such as bond pads formed on the chips are arranged toward the same direction and facilitate shortening of the bonding wires, thereby enhancing electrical transmission and performances for the semiconductor package.

Abstract translation: 提供了一种窗型多芯片半导体封装。 第一芯片和第二芯片安装在形成有开口的基板的表面上，并且第三芯片堆叠在第一和第二芯片上，其中通过开口形成的多个接合线用于将芯片 并将芯片电连接到基板。 芯片被形成在衬底表面上的第一密封剂封装，并且第二密封剂形成在衬底的相对表面上，用于封装接合线。 利用芯片安装在基板的相同表面上，形成在芯片上的接合焊盘等导电元件朝向相同的方向排列，便于连接线的缩短，从而提高半导体封装的电气传输和性能。

公开(公告)号：US06603195B1

公开(公告)日：2003-08-05

申请号：US09605173

申请日：2000-06-28

Applicant: David V. Caletka ,  James L. Carper ,  John P. Cincotta ,  Kibby B. Horsford ,  Gary H. Irish ,  John J. Lajza, Jr. ,  Gordon C. Osborne, Jr. ,  Charles R. Ramsey ,  Robert M. Smith ,  Michael J. Vadnais

Inventor： David V. Caletka ,  James L. Carper ,  John P. Cincotta ,  Kibby B. Horsford ,  Gary H. Irish ,  John J. Lajza, Jr. ,  Gordon C. Osborne, Jr. ,  Charles R. Ramsey ,  Robert M. Smith ,  Michael J. Vadnais

IPC: H01L2350

CPC classification number: H01L23/16 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor module includes a semiconductor chip, a lead frame having lead fingers, and a down set member within an encapsulant for reduce warpage and providing a more planar package by balancing thermal stress between the lead fingers and the encapsulant. The down set member can be a bent portion of the lead frame. It can also be a separate body, such as a dummy semiconductor chip.

Abstract translation: 半导体模块包括半导体芯片，具有引线指的引线框架和用于减少翘曲的密封剂内的向下固定构件，并且通过平衡引线指和密封剂之间的热应力来提供更平面的封装。 下降组件可以是引线框架的弯曲部分。 它也可以是单独的体，例如虚拟半导体芯片。

公开(公告)号：US06414391B1

公开(公告)日：2002-07-02

申请号：US09343746

申请日：1999-06-30

Applicant: David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

Inventor： David J. Corisis ,  Walter L. Moden ,  Leonard E. Mess ,  Larry D. Kinsman

IPC: H01L2350

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract translation: 可堆叠形成高密度组件的球栅阵列封装以及堆叠球栅阵列的方法。 球栅阵列封装包括柔性或刚性衬底。 球栅阵列封装还包括用于连接到半导体器件的电路的阻抗的基本匹配的布置。

公开(公告)号：US06351841B1

公开(公告)日：2002-02-26

申请号：US09531725

申请日：2000-03-21

Applicant: Andrew C. Tickle

Inventor： Andrew C. Tickle

IPC: H01L2350

CPC classification number: G06F17/5068

Abstract: A method of creating multi-gate transistors with integrated circuit polygon compactors is disclosed. Specifically, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least one parallel transistor over the diffusion layer of the target transistor, between a gate and contact. The compactor then enforces the new design rules, and adjusts the relative sizes of the parallel transistors as required. The resulting multi-gate transistor structure is much more compact than a single large transistor, providing a more efficient design layout.

Abstract translation: 公开了一种用集成电路多边形压实机制造多栅极晶体管的方法。 具体地说，为了在设计迁移期间晶体管的尺寸增加时提供更有效的布局，通过在目标晶体管的扩散层之间插入至少一个并联晶体管，形成栅极和 联系。 然后，压实机执行新的设计规则，并根据需要调整并联晶体管的相对尺寸。 所得到的多栅极晶体管结构比单个大晶体管更紧凑，提供了更有效的设计布局。

公开(公告)号：US06245448B1

公开(公告)日：2001-06-12

申请号：US08190729

申请日：1994-02-02

Applicant: Donald Charles Abbott

Inventor： Donald Charles Abbott

IPC: H01L2350

CPC classification number: H01L24/97 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48664 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S428/929 ,  Y10T428/12875 ,  Y10T428/1291 ,  Y10T428/12944 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A palladium plated lead frame (34) for integrated circuit devices has a nickel strike (36) and a palladium/nickel alloy layer (38) separating the copper base metal (28) from the nickel intermediate layer (40) in order to prevent a galvanic potential from drawing copper ions from the base metal layer (28) to the top layer (42). The nickel strike (36) and palladium/nickel alloy layer (38) also reduce the number of paths through which a copper ion could migrate to the top surface resulting in corrosion.

Abstract translation: 用于集成电路器件的镀钯引线框架（34）具有镍触击（36）和将铜基体金属（28）与镍中间层（40）分离的钯/镍合金层（38），以防止 从铜基离子从基底金属层（28）吸收到顶层（42）的电位。 镍触击（36）和钯/镍合金层（38）也减少了铜离子可迁移到顶表面的路径的数量，导致腐蚀。

公开(公告)号：US06787920B2

公开(公告)日：2004-09-07

申请号：US10179761

申请日：2002-06-25

Applicant: Dudi Amir

Inventor： Dudi Amir

IPC: H01L2350

CPC classification number: H01L23/5386 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: A carrier substrate comprising a non-conductive substrate, one or more conductive regions on, under or within the non-conductive substrate, and a plurality of pads, selectively coupled with the conductive regions, to receive and couple with conductive elements of a component, wherein at least one pad is configured to receive and couple with two or more conductive elements of the component.

Abstract translation: 包括非导电衬底的载体衬底，在非导电衬底上，下面或内部的一个或多个导电区域，以及与导电区域选择性耦合以接收和耦合组件的导电元件的多个焊盘， 其中至少一个焊盘被配置为接收和耦合所述部件的两个或多个导电元件。