公开(公告)号：US09847775B2

公开(公告)日：2017-12-19

申请号：US15279727

申请日：2016-09-29

申请人： SK hynix Inc.

发明人： Hae Kang Jung

IPC分类号： H03K3/356 ,  H03K3/3562 ,  H03K5/15 ,  H03M9/00

CPC分类号： H03M9/00 ,  H03K3/356095 ,  H03K5/15013

摘要： A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

公开(公告)号：US08107587B2

公开(公告)日：2012-01-31

申请号：US12736488

申请日：2009-03-27

申请人： Patrick Zebedee ,  Jaganath Rajendra

发明人： Patrick Zebedee ,  Jaganath Rajendra

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  H03K3/356017 ,  H03K3/356086 ,  H03K3/356095 ,  H03K3/3562

摘要： A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

摘要翻译： 数字逻辑电路包括具有相同导电类型的多个晶体管。 在至少一个实施例中，第一晶体管具有分别连接到第一电路节点，第二电路节点和第一电源线的源极，栅极和漏极。 第二晶体管具有分别连接到第二节点，第一节点和第一供电线的源极，栅极和漏极。 第三晶体管具有连接到第一节点的漏极。 第四晶体管分别具有连接到第三电路节点和第二电路节点的栅极和漏极。 第五晶体管分别具有连接到第一和第三节点的栅极和漏极。 这种电路可以用作例如有源矩阵寻址装置的移位寄存器中的锁存器。

公开(公告)号：US5471149A

公开(公告)日：1995-11-28

申请号：US300220

申请日：1994-09-06

申请人： Hideki Usuki

发明人： Hideki Usuki

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K3/356156 ,  H03K3/35606 ,  H03K3/356095

摘要： A voltage level shifting circuit which enables realization of high sensitivity input, high speed, and large output amplitude with a low power consumption, wherein a flipflop is constituted by two CMOS inverters, INV.sub.1 and INV.sub.2, the power voltage sides of the CMOS inverters are used as the inputs of the signals, transfer gates are connected between the input terminals of the input signals and the input terminals of the CMOS inverters, and the transfer gates are turned on and off by the same clock signal CLK.

摘要翻译： 一种电压电平移动电路，其能够以低功耗实现高灵敏度输入，高速度和大输出幅度，其中触发器由两个CMOS反相器INV1和INV2构成，CMOS反相器的电源电压侧被使用 作为信号的输入，传输门连接在输入信号的输入端和CMOS反相器的输入端之间，并且传输门通过相同的时钟信号CLK导通和截止。

公开(公告)号：US5287015A

公开(公告)日：1994-02-15

申请号：US824029

申请日：1992-01-22

申请人： Miki Z. Moyal ,  Ryan E. Feemster

发明人： Miki Z. Moyal ,  Ryan E. Feemster

IPC分类号： H03K3/356 ,  H03K5/24 ,  H03K17/16

CPC分类号： H03K3/356095 ,  H03K3/356034 ,  H03K3/35613

摘要： An apparatus is disclosed for comparing a first input signal with a second input signal and generating an output signal representative of that comparison in response to a system clock signal. The apparatus comprises a plurality of amplifying circuits. A first amplifying circuit generates a pair of first amplifier signals representative of the input signals applied to the apparatus. A second amplifying circuit receives the pair of first amplifier signals and generates a pair of second amplifier signals representative of the pair of first amplifier signals. A delay circuit receives the system clock signal and generates a delayed clock signal which follows the system clock signal by predetermined interval. A first switching circuit is operatively connected across the first amplifier outputs and responds to the system clock signal. A second switching circuit is operatively connected across the second amplifier outputs and is responsive to the delayed clock signal. The predetermined interval between the system clock signal and the delayed clock signal is preferably appropriate to facilitate substantial decay of noise introduced into the pair of first amplifier signals by the opening of the first switching circuit.

摘要翻译： 公开了一种用于将第一输入信号与第二输入信号进行比较并根据系统时钟信号产生表示该比较的输出信号的装置。 该装置包括多个放大电路。 第一放大电路产生代表施加到该装置的输入信号的一对第一放大器信号。 第二放大电路接收一对第一放大器信号，并产生代表一对第一放大器信号的一对第二放大器信号。 延迟电路接收系统时钟信号，并以预定间隔产生跟随系统时钟信号的延迟时钟信号。 第一开关电路可操作地连接在第一放大器输出端上并响应于系统时钟信号。 第二切换电路可操作地连接在第二放大器输出端上并响应延迟的时钟信号。 系统时钟信号和延迟的时钟信号之间的预定间隔优选地适于通过打开第一开关电路来促进引入一对第一放大器信号的噪声的实质衰减。

公开(公告)号：US4692642A

公开(公告)日：1987-09-08

申请号：US753715

申请日：1985-07-10

申请人： Yukio Fukuzo ,  Yasukazu Inoue

发明人： Yukio Fukuzo ,  Yasukazu Inoue

IPC分类号： G11C11/409 ,  G11C11/4094 ,  H03K3/356 ,  H03K19/017

CPC分类号： H03K3/35606 ,  G11C11/4094 ,  H03K19/01742 ,  H03K3/356095

摘要： An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.

摘要翻译： 一种改进的有源上拉电路，其可以以较少数量的元件制造并且以小的功耗进行操作。 在刷新电压端子和要上拉的真实电路节点之间设置第一开关。 提供由互补电路节点的电位控制的第二开关用于可操作地放电第一开关的控制电极的电荷。 通过电容器将上拉时钟施加到第一开关的控制电极。

公开(公告)号：US4031522A

公开(公告)日：1977-06-21

申请号：US594579

申请日：1975-07-10

申请人： John Anthony Reed ,  Joel Allen Karp

发明人： John Anthony Reed ,  Joel Allen Karp

IPC分类号： G11C11/41 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/419 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356017 ,  G11C11/404 ,  G11C11/4091 ,  H03K3/356095

摘要： This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a "zero" level of a cell and also leave a precharged "one" level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.

摘要翻译： 本公开涉及一种与单晶体管单元的集成电路存储器阵列一起使用的高阻抗再生差动读出放大器。 读出放大器中的每一个由交叉耦合的锁存器形成，该锁存器由源极跟随器连接到各个列，并且从耦合到相应列的锁存驱动器写回门的引线形成，以便恢复单元的“零”电平， 通过对适当的柱进行充电，用电池预充电“一”电平。 各列最初被预先充电和平衡，然后由负向信号驱动。

公开(公告)号：US4031415A

公开(公告)日：1977-06-21

申请号：US624813

申请日：1975-10-22

申请人： Donald J. Redwine ,  Norishisa Kitagawa

发明人： Donald J. Redwine ,  Norishisa Kitagawa

IPC分类号： G11C11/413 ,  G11C11/408 ,  G11C17/12 ,  H03K3/356 ,  H03K3/286 ,  G11C11/40 ,  H03K3/353 ,  H03K5/20

CPC分类号： G11C11/4082 ,  G11C17/12 ,  H03K3/356095

摘要： Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.

摘要翻译： 公开了在MOS集成电路中实现的用于半导体存储器等的地址缓冲电路。 MOS晶体管的交叉耦合差分对用于在短时间窗口期间检测地址输入，并且从交叉耦合对的状态产生内部地址信号。

公开(公告)号：US20170331462A1

公开(公告)日：2017-11-16

申请号：US15279727

申请日：2016-09-29

申请人： SK hynix Inc.

发明人： Hae Kang JUNG

IPC分类号： H03K3/3562 ,  H03M9/00 ,  H03K5/15

CPC分类号： H03M9/00 ,  H03K3/356095 ,  H03K5/15013

摘要： A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

公开(公告)号：US4777623A

公开(公告)日：1988-10-11

申请号：US869653

申请日：1986-06-02

申请人： Yukihiko Shimazu ,  Eiichi Teraoka

发明人： Yukihiko Shimazu ,  Eiichi Teraoka

IPC分类号： G11C7/00 ,  G06F1/24 ,  G11C11/401 ,  G11C11/41 ,  H03K3/037 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356095 ,  H03K3/35606

摘要： A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.

摘要翻译： 存储电路14包括在正常操作时选择其阈值电压高于输出电压的MOS晶体管15。 因此，在正常工作的情况下，MOS晶体管15截止，比例锁存器4进行普通存储操作。 同时，如果电源12的输出电压升高，则MOS晶体管15导通，将数据输入线6a的电位下拉到比率锁存器。 因此，比例闩锁4被强制设定。

公开(公告)号：US4539495A

公开(公告)日：1985-09-03

申请号：US613480

申请日：1984-05-24

申请人： Michael J. Demler

发明人： Michael J. Demler

IPC分类号： G01R19/165 ,  G01R19/00 ,  G11C7/06 ,  G11C11/419 ,  H03K3/0233 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03K3/023

CPC分类号： G01R19/0038 ,  G11C7/065 ,  H03K3/35606 ,  H03K3/356095 ,  H03K3/356156 ,  H03K5/249

摘要： The voltage comparator includes a first and a second voltage supply terminal, and a first and a second output node. A first current source is connected between the first supply terminal and the first output node. A first field effect transistor of one channel conductivity type is connected between the first output node and the second supply terminal. The gate of the first transistor is connected to the second output node. A second current source is connected between the first supply terminal and the second output node. A second field effect transistor of the one conductivity is connected between the second output node and the second supply terminal. The gate of the second transistor is connected to the first output node. During a first period of time the first and second output nodes and the capacitances of the gates of the first and second transistors connected thereto are maintained at the potential of the second supply terminal by switches connected thereacross. At the end of the first period the switches are opened allowing the first and second output nodes to charge. Simultaneously charge proportional to a first signal voltage is supplied to the first output node and charge proportional to a second signal voltage is supplied to the second output node. The node which receives the greater charge rapidly charges toward the voltage of the first supply terminal and the node which receives the smaller charge is maintained at the potential of the second supply terminal. Thus, an indication is obtained of the greater of the two voltages.

摘要翻译： 电压比较器包括第一和第二电压供给端子以及第一和第二输出节点。 第一电流源连接在第一电源端子和第一输出节点之间。 一个沟道导电类型的第一场效应晶体管被连接在第一输出节点和第二供电端之间。 第一晶体管的栅极连接到第二输出节点。 第二电流源连接在第一电源端子和第二输出节点之间。 一个电导率的第二场效应晶体管连接在第二输出节点和第二电源端子之间。 第二晶体管的栅极连接到第一输出节点。 在第一时间段期间，连接到第一和第二输出节点的第一和第二晶体管的栅极的电容通过连接在其上的开关保持在第二电源端子的电位。 在第一周期结束时，开关被打开，允许第一和第二输出节点充电。 与第一信号电压成比例的同时充电被提供给第一输出节点，并且与第二信号电压成正比的电荷被提供给第二输出节点。 接收较大电荷的节点向第一电源端子的电压快速充电，并且接收较小电荷的节点保持在第二电源端子的电位。 因此，获得两个电压中较大者的指示。