摘要:
A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.
摘要:
A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.
摘要:
A voltage level shifting circuit which enables realization of high sensitivity input, high speed, and large output amplitude with a low power consumption, wherein a flipflop is constituted by two CMOS inverters, INV.sub.1 and INV.sub.2, the power voltage sides of the CMOS inverters are used as the inputs of the signals, transfer gates are connected between the input terminals of the input signals and the input terminals of the CMOS inverters, and the transfer gates are turned on and off by the same clock signal CLK.
摘要:
An apparatus is disclosed for comparing a first input signal with a second input signal and generating an output signal representative of that comparison in response to a system clock signal. The apparatus comprises a plurality of amplifying circuits. A first amplifying circuit generates a pair of first amplifier signals representative of the input signals applied to the apparatus. A second amplifying circuit receives the pair of first amplifier signals and generates a pair of second amplifier signals representative of the pair of first amplifier signals. A delay circuit receives the system clock signal and generates a delayed clock signal which follows the system clock signal by predetermined interval. A first switching circuit is operatively connected across the first amplifier outputs and responds to the system clock signal. A second switching circuit is operatively connected across the second amplifier outputs and is responsive to the delayed clock signal. The predetermined interval between the system clock signal and the delayed clock signal is preferably appropriate to facilitate substantial decay of noise introduced into the pair of first amplifier signals by the opening of the first switching circuit.
摘要:
An improved active pull-up circuit which can be fabricated with reduced number of elements and operate with a small power consumption.A first switch is provided between a refresh voltage terminal and a true circuit node to be pulled-up. A second switch controlled by a potential of a complementary circuit node is provided for operatively discharging the charge of a control electrode of the first switch. A pull-up clock is applied via a capacitor to the control electrode of the first switch.
摘要:
This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a "zero" level of a cell and also leave a precharged "one" level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.
摘要:
Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.
摘要:
A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.
摘要:
A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.
摘要:
The voltage comparator includes a first and a second voltage supply terminal, and a first and a second output node. A first current source is connected between the first supply terminal and the first output node. A first field effect transistor of one channel conductivity type is connected between the first output node and the second supply terminal. The gate of the first transistor is connected to the second output node. A second current source is connected between the first supply terminal and the second output node. A second field effect transistor of the one conductivity is connected between the second output node and the second supply terminal. The gate of the second transistor is connected to the first output node. During a first period of time the first and second output nodes and the capacitances of the gates of the first and second transistors connected thereto are maintained at the potential of the second supply terminal by switches connected thereacross. At the end of the first period the switches are opened allowing the first and second output nodes to charge. Simultaneously charge proportional to a first signal voltage is supplied to the first output node and charge proportional to a second signal voltage is supplied to the second output node. The node which receives the greater charge rapidly charges toward the voltage of the first supply terminal and the node which receives the smaller charge is maintained at the potential of the second supply terminal. Thus, an indication is obtained of the greater of the two voltages.