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    Transmit driver circuit
    4.
    发明授权
    Transmit driver circuit 有权
    发射驱动电路

    公开(公告)号：US08866514B2

    公开(公告)日：2014-10-21

    申请号：US14078190

    申请日：2013-11-12

    申请人： STMicroelectronics (Canada) Inc.

    发明人： Anton Pelteshki ,  Hock Khor

    IPC分类号： H03B1/00 ,  H04L25/02 ,  H03F3/45 ,  H03K3/01

    CPC分类号： H03K3/01 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2203/45394 ,  H03F2203/45712 ,  H04L25/0266 ,  H04L25/0276 ,  H04L25/0282

    摘要： A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

    摘要翻译： 驱动器电路包括差分输入，差分输出，偏置节点，具有耦合到负输出节点的第一节点的第一T形线圈和耦合到电源电压源的第二节点，第二T形线圈具有 耦合到正输出节点的第一节点和耦合到电源电压源的第二节点，具有耦合在第一T形线圈的中心抽头和第一中间节点之间的电流通路的第一晶体管，具有电流 耦合在第二T形线圈的中心抽头和第二中间节点之间的路径，具有耦合在第一中间节点和地之间的电流路径的第三晶体管，以及连接在第二中间节点和地之间的电流路径的第四晶体管 。

    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
    8.
    发明授权
    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
    具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元

    公开(公告)号：US07327204B2

    公开(公告)日：2008-02-05

    申请号：US11640079

    申请日：2006-12-15

    申请人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    发明人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    IPC分类号： H04B3/04

    CPC分类号： H03F3/45183 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45652 ,  H03F2203/45688 ,  H03F2203/45712

    摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

    摘要翻译： 抽头延迟链包括多个延迟单元，其中每个单元具有至少两个输出抽头：用于将延迟的信号馈送到链中的下一个单元的初级延迟单元，以及用于馈送稍微不同的延迟信号的次级输出抽头 到乘法器单元，使得略微不同的延迟信号可以乘以加权系数。 每个延迟单元中的输出抽头分开允许相应的负载电容分流。 延迟单元的每个输出抽头加载的电容小于如果分裂抽头被集中在一起作为公共节点而不得不以其他方式驱动的电容。 每个分接抽头的减小的负载电容允许更宽的频率响应范围。 抽头延迟链可用于形成前馈均衡器（FFE），该前馈均衡器还包括加法器和多个乘法器，每个乘法器分别接收延迟的输入信号（（延迟）） 链中相应的延迟单元的辅助输出抽头，并且每个输出相应的延迟加权乘积信号（Pi）给加法器。

    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
    9.
    发明申请
    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
    具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元

    公开(公告)号：US20060044061A1

    公开(公告)日：2006-03-02

    申请号：US10928420

    申请日：2004-08-27

    申请人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    发明人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45652 ,  H03F2203/45688 ,  H03F2203/45712

    摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

    摘要翻译： 抽头延迟链包括多个延迟单元，其中每个单元具有至少两个输出抽头：用于将延迟的信号馈送到链中的下一个单元的初级延迟单元，以及用于馈送稍微不同的延迟信号的次级输出抽头 到乘法器单元，使得略微不同的延迟信号可以乘以加权系数。 每个延迟单元中的输出抽头分开允许相应的负载电容分流。 延迟单元的每个输出抽头加载的电容小于如果分裂抽头被集中在一起作为公共节点而不得不以其他方式驱动的电容。 每个分接抽头的减小的负载电容允许更宽的频率响应范围。 抽头延迟链可用于形成前馈均衡器（FFE），该前馈均衡器还包括加法器和多个乘法器，每个乘法器分别接收延迟的输入信号（（延迟）） 链中相应的延迟单元的辅助输出抽头，并且每个输出相应的延迟加权乘积信号（Pi）给加法器。