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1.发明授权
公开(公告)号：US5521938A
公开(公告)日：1996-05-28
申请号：US276073
申请日：1994-07-01
Applicant: Kenneth A. Stewart , Robert T. Love
Inventor： Kenneth A. Stewart , Robert T. Love
CPC classification number: H04B1/0021 , H03D3/007 , H04B1/0003 , H04B1/0032 , H04B1/0046 , H04B1/26 , H03D2200/005 , H03D2200/0056 , H03D2200/006 , H03D2200/0068 , H03D2200/0072 , H03D2200/008
Abstract: An efficient apparatus for performing frequency conversion from a final IF frequency to a baseband frequency is described. A counter (401) generates two logical signals G1 (402) and G2 (403) which are passed to an exclusive-OR gate (404) and a multiplexer (406). When a control signal (411) is deasserted, multiplexer (406) passes signal G1 to I1 and signal G2 to I2; when control signal (411) is asserted, multiplexer (406) passes binary signal G1 to I2 (410) and signal G2 to I1 (407). Similarly, multiplexer (405) swaps its input real and imaginary samples when the output of exclusive-OR gate (404) is asserted; otherwise, it performs no operation on its input samples. Signals I1 (407) and I2 (410) are used to control arithmetic inverters (408) and (409) respectively. When the controlling signal for either inverter is asserted, the inverter performs arithmetic inversion, otherwise it performs no operation.
Abstract translation: 描述用于从最终IF频率到基带频率执行频率转换的有效装置。 计数器（401）生成传递给异或门（404）和多路复用器（406）的两个逻辑信号G1（402）和G2（403）。 当控制信号（411）被断言时，多路复用器（406）将信号G1通过信号G1到信号G2到I2; 当控制信号（411）被断言时，多路复用器（406）将二进制信号G1传递给I2（410）和信号G2到I1（407）。 类似地，当异或门（404）的输出被断言时，多路复用器（405）交换其输入的实数和虚数样本; 否则，它对其输入样本不执行任何操作。 信号I1（407）和I2（410）分别用于控制算术逆变器（408）和（409）。 当任一变频器的控制信号有效时，变频器进行算术反转，否则不执行。
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公开(公告)号：US4733403A
公开(公告)日：1988-03-22
申请号：US861958
申请日：1986-05-12
Applicant: Daniel A. Simone
Inventor： Daniel A. Simone
CPC classification number: H03D3/007 , H03D2200/0056 , H03D2200/006 , H03D2200/009 , H03D2200/0092 , H03D3/006 , H03D7/165
Abstract: Disclosed is a digital zero-IF selectivity section circuit which operates on a recovered input signal, digitally clocked by a first clock at a rate of FS, in receiver device. The circuit uses a second clock operating at a lesser rate than the first clock to clock an N-order FIR digital filtering means to selectively band-limit the frequency spectrum of the recovered input signal. A second digital filtering means is coupled to the output of the first FIR digital filtering means. The second digital filtering means operates at a clock speed less than or equal to the second clock speed. The second digital filtering means is used to further selectively band-limit the frequency spectrum of the recovered input signal.
Abstract translation: 公开了一种数字零中频选择部分电路，其在接收机设备中以恢复的输入信号进行操作，该恢复的输入信号由FS的速率由第一时钟数字地计时。 电路使用以比第一时钟更低的速率操作的第二时钟来对N阶FIR数字滤波装置进行时钟以选择性地限制所恢复的输入信号的频谱。 第二数字滤波装置耦合到第一FIR数字滤波装置的输出端。 第二数字滤波装置以小于或等于第二时钟速度的时钟速度工作。 第二数字滤波装置用于进一步选择性地限制所恢复的输入信号的频谱。
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公开(公告)号：US09985650B2
公开(公告)日：2018-05-29
申请号：US15392491
申请日：2016-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Suvam Nandi , Jaiganesh Balakrishnan
CPC classification number: H03M7/6047 , H03D7/165 , H03D2200/0056 , H03H17/0664 , H03M7/3059
Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US20170324423A1
公开(公告)日：2017-11-09
申请号：US15392491
申请日：2016-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal TANGUDU , Suvam NANDI , Jaiganesh BALAKRISHNAN
CPC classification number: H03M7/6047 , H03D7/165 , H03D2200/0056 , H03H17/0664 , H03M7/3059
Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US5910752A
公开(公告)日：1999-06-08
申请号：US987307
申请日：1997-12-09
Applicant: Daniel Filipovic , Saed G. Younis
Inventor： Daniel Filipovic , Saed G. Younis
CPC classification number: H03D3/006 , H03D2200/005 , H03D2200/0056 , H03D2200/0062 , H03D2200/0064
Abstract: An receiver receives, amplifies, filters, and downconverts an RF signal to obtain an FM signal. The FM signal is then limited by a limiter and sampled by an ADC. The FM samples from the ADC are provided to an edge detector which detects transitions in the FM samples. The transitions correspond to zero crossings in the FM signal. The time period between the zero crossings, or the cycle width, is measured with a counter to determine the instantaneous frequency f.sub.c of the FM signal. The demodulated output is proportional to the instantaneous frequency which can be determined from the measured cycle periods as f.sub.c =1/2T.sub.c, f.sub.c .apprxeq.-.alpha.T.sub.c, or f.sub.c .varies.T.sub.c, where T.sub.c is the measured cycle period, and .alpha. is a constant based on the slope of 1/2T.sub.c,avg, where T.sub.c,avg is the average cycle period. The sample rate of the demodulated output can be reduced, through resampling, to minimize power consumption in the subsequent signal processing blocks.
Abstract translation: 接收机接收，放大，滤波和下变频RF信号以获得FM信号。 然后，FM信号由限幅器限制并由ADC采样。 来自ADC的FM采样被提供给检测FM样本中的转变的边缘检测器。 转换对应于FM信号中的过零点。 通过计数器测量过零点之间的时间周期或周期宽度，以确定FM信号的瞬时频率fc。 解调输出与瞬时频率成比例，可以从测量的周期周期确定为fc = + E，fra 1/2 + EE Tc，fc APPROX-αTc或fc比例Tc，其中Tc是测量周期周期 ，α是基于+ E的斜率的常数，f1 / 2 + EE Tc，avg，其中Tc，avg是平均循环周期。 可以通过重采样来减小解调输出的采样率，以使后续信号处理模块中的功耗最小化。
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Patent Agency Ranking6.发明授权Receiver with quadrature decimation stage, method of processing digital signals 失效具有正交抽取级的接收机，数字信号处理方法
公开(公告)号：US5784414A
公开(公告)日：1998-07-21
申请号：US523704
申请日：1995-09-05
Applicant: Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
Inventor： Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
CPC classification number: H03D3/007 , H03D2200/005 , H03D2200/0056 , H03D3/006
Abstract: In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).
Abstract translation: 在接收机中，接收信号以较高的采样频率被数字化（5）。 模拟滤波器（2,4）可以防止混叠。 数字化接收信号通过分路器（100）施加到正交数字信号处理器（9,10,11,12）。 在该处理器中，选择并解调所需的载波。 分离器（100）根据第一和第二变换函数（H1，H2）转换数字化的接收信号，以分别获得同相和正交分量（xi，yi）。 分路器中的采样频率减小（130,140）。 变换函数（H1，H2）的相位和幅度之间的具体关系可以防止混叠。 这种关系可以用相对简单的数字滤波器（110,120）来实现。
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公开(公告)号：US5483555A
公开(公告)日：1996-01-09
申请号：US52703
申请日：1993-04-27
Applicant: Shinji Hattori
Inventor： Shinji Hattori
CPC classification number: H03D3/006 , H03D2200/0029 , H03D2200/005 , H03D2200/0056 , H03D2200/006
Abstract: A phase adjusting circuit for a demodulator is provided. The circuit comprises an A/D converter for sampling an input analog signal at an interval shorter than the Nyquist interval and converting the sampled analog signal to a digital signal, a digital filter for narrowing the frequency band of the digital signal to output a filtered digital signal, a digital sampling/holding circuit for decimating sampling components of the filtered digital signal to output a decimated digital signal, and a phase locked loop circuit for detecting a phase error of the decimated digital signal and controlling the number of sampling intervals to be skipped by the digital sampling/holding circuit.
Abstract translation: 提供了一种用于解调器的相位调整电路。 该电路包括A / D转换器，用于以比奈奎斯特间隔更短的间隔对输入模拟信号进行采样，并将采样的模拟信号转换为数字信号，数字滤波器用于使数字信号的频带变窄以输出滤波数字 信号，用于抽取滤波数字信号的采样分量以输出抽取数字信号的数字采样/保持电路，以及用于检测抽取数字信号的相位误差并控制要跳过的采样间隔数的锁相环电路 由数字采样/保持电路。
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8.发明授权
公开(公告)号：US5204635A
公开(公告)日：1993-04-20
申请号：US838738
申请日：1992-03-11
Applicant: Yasuhito Takeuchi
Inventor： Yasuhito Takeuchi
CPC classification number: H03D3/20 , H03M1/504 , H03M3/00 , H03D2200/0047 , H03D2200/0056 , H03D2200/0082
Abstract: An FM demodulator which generates a modulated object signal directly in digital form, wherein an input FM signal is phase detected, then converted to digital form, then quantized into a pulse density modulated binary signal using a clock reference signal having a frequency which is not correlated to the frequency of the input FM signal, and then the signal is filtered at the clock reference signal and outputted as the digital word output. Advantageously, by using the non-correlated clock reference signal, the signal to noise ratio is improved by a substantial factor.
Abstract translation: PCT No.PCT / JP91 / 00917 Sec。 371日期：1992年3月11日 102（e）1992年3月11日PCT PCT 1991年7月9日PCT公布。 第WO92 / 01332号公报 一种FM解调器，其直接以数字形式生成调制对象信号，其中输入FM信号被相位检测，然后转换成数字形式，然后使用时钟参考信号量化为脉冲密度调制二进制信号 具有与输入FM信号的频率不相关的频率，然后在时钟参考信号处对信号进行滤波并作为数字字输出输出。 有利的是，通过使用非相关的时钟参考信号，通过实质的因素提高了信噪比。
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公开(公告)号：US4707666A
公开(公告)日：1987-11-17
申请号：US886203
申请日：1986-07-15
Applicant: Heinrich Pfeifer , Rainer Schweer
Inventor： Heinrich Pfeifer , Rainer Schweer
CPC classification number: H03D3/006 , H03D2200/005 , H03D2200/0056 , H03D2200/0064
Abstract: A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.
Abstract translation: 数字频率解调器电路在相应的现有技术的模拟电路中基于在给定时间段内确定带限输入信号的过零次数的原理起作用。 该电路包括一个模拟 - 数字转换器，三个延迟元件，两个边缘检测器，一个向上/向下计数器，两个arcsin只读存储器，1/2乘法器和多加法器。
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公开(公告)号：US09148162B2
公开(公告)日：2015-09-29
申请号：US14595396
申请日：2015-01-13
Applicant: Guzik Technical Enterprises
Inventor： Anatoli B. Stein , Semen P. Volfbeyn
CPC classification number: H04L27/01 , H03D1/2245 , H03D7/165 , H03D2200/005 , H03D2200/0056
Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.
Abstract translation: 具有均衡的数字下变频器包括模数转换器（ADC），分频器，FIR-抽取器-I，FIR-抽取器-Q和频率校正器。 在操作中，在一些预处理之后，FIR-抽取器-1执行等价于均衡序列的信号变换，处理的信号乘以转换频率的正弦波和低通滤波，并且FIR-抽取器-Q执行信号 转换等效于均衡序列，将处理后的信号乘以转换频率的正弦波，相移90°和低pas滤波。 经变换的信号被施加到频率校正器，该频率校正器相对于所施加的模拟输入信号的标称载波频率提供预定值的频移，并且产生同相输出和正交输出。
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