公开(公告)号：US4926133A

公开(公告)日：1990-05-15

申请号：US274263

申请日：1988-11-21

申请人： Takashi Koga

发明人： Takashi Koga

IPC分类号： H03D3/00 ,  H03D3/06 ,  H03D3/20 ,  H03K5/1532

CPC分类号： H03D3/20 ,  H03D2200/0039

摘要： An FM signal demodulator for converting the frequency of an input signal to a corresponding voltage. The demodulator includes a delay circuit responsive to the input signal for delaying the phase of the input signal by a fixed time, an exclusive-OR gate responsive to the input signal and the delayed phase signal from the delay circuit for outputting a pulse signal having a duration corresponding to the fixed time and an LPF responsive to the pulse signal for generating an output signal having a level which changes in response to changes in the frequency of the input signal.

摘要翻译： FM信号解调器，用于将输入信号的频率转换成相应的电压。 解调器包括响应于输入信号的延迟电路，用于将输入信号的相位延迟固定时间，响应于输入信号的异或门和来自延迟电路的延迟相位信号，用于输出具有 对应于固定时间的持续时间和响应于脉冲信号的LPF，用于产生具有响应于输入信号的频率变化而改变的电平的输出信号。

公开(公告)号：US4839606A

公开(公告)日：1989-06-13

申请号：US84662

申请日：1987-08-11

申请人： David B. Hallock

发明人： David B. Hallock

IPC分类号： H03B29/00 ,  H03D3/20

CPC分类号： H03D3/20 ,  H03B29/00 ,  H03D2200/0039

摘要： Audio beat notes produced by sampling a square wave in a digital quadrature FM demodulator are reduced by adding random noise, or dither, to the signal to be demodulated to randomly vary the width of successive pulses in the square wave.

摘要翻译： 通过对要解调的信号添加随机噪声或抖动来在数字正交FM解调器中采样方波产生的音频节拍被减少以随机地改变方波中连续脉冲的宽度。

公开(公告)号：US4628272A

公开(公告)日：1986-12-09

申请号：US655822

申请日：1984-10-01

申请人： Walter L. Davis ,  Yolanda Prieto

发明人： Walter L. Davis ,  Yolanda Prieto

IPC分类号： H03D3/06 ,  H03D3/02 ,  H03D3/20

CPC分类号： H03D3/20 ,  H03D2200/0009 ,  H03D2200/0039 ,  H03D2200/0082 ,  H03D2200/0096

摘要： An inductorless quadrature demodulator for frequency modulated signals is disclosed. A limited FM signal is passed through an active filter (26) and a phase shift network (30) to produce a quadrature signal. The limited FM signal is compared with the quadrature signal in an EXCLUSIVE OR gate (24) and then low pass filtered (36) to obtain recovered audio. The active filter (26) includes a transconductance amplifier (60) whose center frequency can be adjusted by appropriate adjustment of the amplifier's bias current. The bias current is temperature compensated to allow operation of the demodulator over a wide temperature range.

摘要翻译： 公开了一种用于调频信号的无电感正交解调器。 有限的FM信号通过有源滤波器（26）和相移网络（30）以产生正交信号。 将有限的FM信号与异或门（24）中的正交信号进行比较，然后低通滤波（36）以获得恢复的音频。 有源滤波器（26）包括跨导放大器（60），其中心频率可以通过适当调整放大器的偏置电流来调节。 偏置电流进行温度补偿，以允许解调器在宽温度范围内工作。

公开(公告)号：US4435682A

公开(公告)日：1984-03-06

申请号：US276600

申请日：1981-06-23

申请人： Robert Boudault ,  Gerard Pouzoullic

发明人： Robert Boudault ,  Gerard Pouzoullic

IPC分类号： H03D3/06 ,  H03D3/02 ,  H03D3/20 ,  H03K9/06 ,  H04L27/14 ,  H04L27/156

CPC分类号： H03D3/20 ,  H03K9/06 ,  H04L27/1563 ,  H03D2200/0039 ,  H03D2200/0096

摘要： A frequency demodulator including an "exclusive-OR" circuit receiving two square-wave signals having a frequency corresponding to a frequency-modulated signal, and a delay circuit for delaying one of the square-wave signals before application to the "exclusive-OR" circuit, by a delay varying versus frequency in such a way that the absolute value of the phase difference between the square-wave signals varies at most from 0.degree. to 180.degree. inversely with respect to changes in frequency. The output signal of the demodulator is supplied by a low-pass filter connected to the output of the "exclusive-OR" circuit.

摘要翻译： 一种频率解调器，包括接收具有与频率调制信号相对应的频率的两个方波信号的“异或”电路，以及延迟电路，用于在施加到“异或”之前将方波信号之一延迟 电路通过延迟变化对频率的方式使得方波信号之间的相位差的绝对值相对于频率变化相反地变化到0°至180°。 解调器的输出信号由连接到“异或”电路的输出的低通滤波器提供。

公开(公告)号：US3022461A

公开(公告)日：1962-02-20

申请号：US82817959

申请日：1959-07-20

申请人： AMPEX

发明人： WILCOX JR DWIGHT D

IPC分类号： H03D3/20

CPC分类号： H03D3/20

公开(公告)号：US5727027A

公开(公告)日：1998-03-10

申请号：US775707

申请日：1996-12-17

申请人： Hiroki Tsuda

发明人： Hiroki Tsuda

IPC分类号： H04L27/22 ,  H03D3/20 ,  H04L27/00 ,  H04L27/233 ,  H04L27/38 ,  H03D3/22

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057

摘要： In a PSK signal demodulation method of demodulating a received signal by sampling processing, one sampling interval is time-divided. A received signal is detected in different carrier frequency offset ranges in the respective time-division intervals. Reception processing is continuously performed in only a time-division interval in which the received signal is detected after the received signal is detected, thereby synchronizing carrier phase. A PSK signal demodulation apparatus is also disclosed.

摘要翻译： 在通过采样处理解调接收信号的PSK信号解调方法中，一个采样间隔被时分。 在各个时分间隔的不同载波频率偏移范围内检测接收信号。 接收处理仅在检测到接收信号之后检测到接收信号的时分间隔中连续进行，从而同步载波相位。 还公开了一种PSK信号解调装置。

公开(公告)号：US5406218A

公开(公告)日：1995-04-11

申请号：US194074

申请日：1994-02-09

申请人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

发明人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

IPC分类号： H03D3/20 ,  H04L27/233

CPC分类号： H04L27/2332 ,  H03D3/20 ,  H03D2200/0039 ,  H03D2200/005

摘要： A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

摘要翻译： 解调电路包括：相位检测电路，用于确定要解调的输入信号和参考信号之间的相位差的绝对值; 二进制相位检测电路，用于将输入信号和参考信号之间的相位超前或滞后转换为相位差的符号; 以及相位解调电路，用于从相位差的绝对值和符号计算输入信号和参考信号之间的相位差量，并对相位差量进行延迟检测; 其中二进制相位检测电路包括产生与相位检测电路的运算延迟相对应的延迟时间的延迟电路; 并且其中所述相位检测电路包括限制内部信号电压的电平限制器电路和参考电压调整电路以校正所述内部信号电压的偏差。

公开(公告)号：US5077538A

公开(公告)日：1991-12-31

申请号：US662385

申请日：1991-02-26

申请人： Holger Gehrt ,  Gunter Hildebrandt ,  Karl-Heinz Rehfeldt

发明人： Holger Gehrt ,  Gunter Hildebrandt ,  Karl-Heinz Rehfeldt

IPC分类号： H03D3/06 ,  H03D3/20

CPC分类号： H03D3/20 ,  H03D2200/0039 ,  H03D2200/0049

摘要： A circuit arrangement which includes an FM demodulator having a delay circuit which subjects the received FM signal to a preset time delay and a signal combining circuit which combines the delayed and undelayed FM signal to derive a combined signal the mean value of which is proportional to the frequency of the FM signal. A low pass filter derives the demodulated signal from such combined signal. The proportionality factor is determined by the preset time delay, which is controllable by a control signal supplied to the delay circuit by a datum level detector which detects a selected datum level of the demodulated signal; for example, the lowest level of such signal. By controlling the time delay in accordance with such datum level, the datum level detector thereby stabilizes the maximum amplitude of the demodulated signal relative to the datum level thereof despite variations in the maximum frequency swing of the received FM signal.

摘要翻译： 一种电路装置，其包括具有延迟电路的FM解调器，该延迟电路使接收到的FM信号进行预设的时间延迟;以及信号组合电路，其组合延迟的和未延时的FM信号，以导出其平均值与 FM信号的频率。 低通滤波器从这种组合信号中导出解调信号。 比例因子由预设的时间延迟确定，该预设时间延迟由控制信号控制，该控制信号由检测所解调的信号的所选择的基准电平的基准电平检测器提供给延迟电路; 例如，这种信号的最低水平。 通过根据这种基准电平来控制时间延迟，因此，尽管基准电平检测器的接收的FM信号的最大频率摆动有所变化，因此基准电平检测器相对于其基准电平稳定了解调信号的最大幅度。

公开(公告)号：US4884037A

公开(公告)日：1989-11-28

申请号：US221117

申请日：1988-07-19

申请人： Akira Sogo

发明人： Akira Sogo

IPC分类号： H03D3/20

CPC分类号： H03D3/20 ,  H03D2200/0039

摘要： A FM demodulation circuit contains an analog-to-digital converter which converts an inputted frequency-modulated (FM) signal into a digital signal of one bit at a timing based on the predetermined clock signal and a differentiation circuit which differentiates the digital signal to thereby output a pulse train whose pulse density is in proportion to a frequency of the inputted FM signal. When the pulse train is supplied to a low-pass filter, the pulse train is converted into an analog signal, which is outputted as a demodulated signal. When the pulse train is supplied to a decimation circuit which includes a weight function generating portion and an accumulator, weighted function values are sequentially accumulated based on the level of the pulse train in the predetermined period so that the demodulated signal can be obtained in the form of a linear pulse code modulated (linear PCM) signal.

摘要翻译： FM解调电路包含模数转换器，其基于预定的时钟信号在定时将输入的调频（FM）信号转换为一位的数字信号，以及将数字信号区分开来的微分电路 输出脉冲密度与输入的FM信号的频率成比例的脉冲串。 当脉冲串被提供给低通滤波器时，脉冲串被转换为模拟信号，该信号作为解调信号输出。 当脉冲序列被提供给包括权重函数产生部分和累加器的抽取电路时，基于脉冲序列的电平在预定周期内顺序地累积加权函数值，使得可以以形式获得解调信号 的线性脉冲编码调制（线性PCM）信号。

公开(公告)号：US3878470A

公开(公告)日：1975-04-15

申请号：US37946973

申请日：1973-07-16

申请人： RCA CORP

发明人： BOLTZ JR CHARLES D

IPC分类号： H03D3/20 ,  H03D3/04

CPC分类号： H03D3/04

摘要： A source of frequency modulated signals is coupled to a coincidence detector by a first and a second signal path. The first and second signal paths have unequal signal delay characteristics so that the coincidence detector provides an output signal comprised of a series of substantially constant width pulses wherein pulse width is determined by the difference in signal delay between the first and second signal paths. A low pass filter is coupled to the coincidence detector for recovering the signal modulation represented by the series of substantially constant width pulses.

摘要翻译： 频率调制信号源通过第一和第二信号路径耦合到符合检测器。 第一和第二信号路径具有不相等的信号延迟特性，使得重合检测器提供由一系列基本上恒定的宽度脉冲组成的输出信号，其中脉冲宽度由第一和第二信号路径之间的信号延迟差确定。 低通滤波器耦合到重合检测器，用于恢复由一系列基本恒定的宽度脉冲表示的信号调制。