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公开(公告)号：US06324233B1
公开(公告)日：2001-11-27
申请号：US09120625
申请日：1998-07-22
申请人： Adrianus Sempel , Eduard F. Stikvoort , Alphons A. M. L. Bruekers , Adrianus W. M. van den Enden , Rudy J. van de Plassche , Gerardus C. M. Gielis
发明人： Adrianus Sempel , Eduard F. Stikvoort , Alphons A. M. L. Bruekers , Adrianus W. M. van den Enden , Rudy J. van de Plassche , Gerardus C. M. Gielis
IPC分类号： H04B1400
CPC分类号： H04N5/4446 , H04B1/1036 , H04B1/26 , H04N5/4401 , H04N5/46
摘要： In a receiver for receiving a modulated carrier (MC) having asymmetrical sidebands (USB,LSB), for example, a TV signal, a synchronous demodulator (SDEM) derives a vectorial baseband signal (VB) from the modulated carrier (MC). A filter (FILT) filters the vectorial baseband signal so as to compensate for the sideband asymmetry, for example, by means of a Nyquist slope. Thus, the sideband asymmetry is compensated at baseband frequencies, rather than at an intermediate frequency, which allows a better quality of reception.
摘要翻译： 在用于接收具有不对称边带（USB，LSB）的例如TV信号的调制载波（MC）的接收机中，同步解调器（SDEM）从调制载波（MC）导出矢量基带信号（VB）。 滤波器（FILT）对矢量基带信号进行滤波，以便例如通过奈奎斯特斜率补偿边带不对称性。 因此，边带不对称性在基带频率而不是中频处得到补偿，这允许更好的接收质量。
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公开(公告)号：US06643502B1
公开(公告)日：2003-11-04
申请号：US09121576
申请日：1998-07-23
IPC分类号： H04B116
CPC分类号： H04N5/4446 , H04B1/1036 , H04B1/26 , H04N5/4401 , H04N5/46
摘要： In a receiver, a tuner (TUN) converts a reception signal (Srf) to an intermediate-frequency signal (Sif). An adjustable frequency converter (AFRC) converts the intermediate-frequency signal (Sif) to an input signal (Sin) for a filter arrangement (FIL) which is capable of providing various frequency responses (Hfil1, Hfil2) associated with different transmission standards. The adjustable frequency converter (AFRC) and the filter arrangement (FIL) may form part of an integrated receiver-circuit (IRC) suitable for many different transmission standards. The tuner (TUN) may provide the intermediate-frequency signal (Sif) at any one of various different intermediate frequencies (IF1, IF2). For any intermediate frequency (IF1,IF2), the adjustable frequency converter (AFRC) can be adjusted in such a way that the filter arrangement (FIL) receives the input signal (Sin) in a frequency range (FR) which is suitably located with respect to its frequency responses (Hfil1, Hfil2). Thus, the adjustable frequency converter (AFRC) allows the use of any one of various different intermediate frequencies and, therefore, allows the use of relatively cheap standard-specific tuners. Thus, it allows relatively cost-efficient implementations.
摘要翻译： 在接收机中，调谐器（TUN）将接收信号（Srf）转换成中频信号（Sif）。 可调变频器（AFRC）将中频信号（Sif）转换为能够提供与不同传输标准相关联的各种频率响应（Hfil1，Hfil2）的滤波器装置（FIL）的输入信号（Sin）。 可调变频器（AFRC）和滤波器装置（FIL）可以构成适合于许多不同传输标准的集成接收机电路（IRC）的一部分。 调谐器（TUN）可以在各种不同的中频（IF1，IF2）中的任何一个处提供中频信号（Sif）。 对于任何中频（IF1，IF2），可调节变频器（AFRC），使得滤波器装置（FIL）在频率范围（FR）中接收输入信号（Sin），该频率范围（FR） 相对于其频率响应（Hfil1，Hfil2）。 因此，可调变频器（AFRC）允许使用各种不同的中频中的任一种，因此允许使用相对便宜的标准特定调谐器。 因此，它允许相对成本有效的实现。
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公开(公告)号：US06175269B1
公开(公告)日：2001-01-16
申请号：US09196089
申请日：1998-11-19
IPC分类号： H03D300
CPC分类号： H03D1/2254 , H03D3/245 , H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0069
摘要： To demodulate a quadrature input signal (Si) (for example, frequency shift) a demodulation unit (DEM) is used, comprising a PLL (P) having a complex mixer (M) and a controlled oscillator (V). Normally, a limiter has to be used to keep the loop gain independent of the amplitude of the quadrature input signal. In the PLL, a divider (DEL) is coupled between the mixer (M) and the oscillator (V) to divide the two mixed components (Sm1, Sm2) of the quadrature signal supplied by the mixer.
摘要翻译： 为了解调正交输入信号（Si）（例如，频移），使用解调单元（DEM），其包括具有复合混频器（M）和受控振荡器（V）的PLL（P）。 通常，必须使用限幅器来保持环路增益，而不受正交输入信号的幅度的影响。 在PLL中，分频器（DEL）耦合在混频器（M）和振荡器（V）之间，以分频由混频器提供的正交信号的两个混合分量（Sm1，Sm2）。
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公开(公告)号：US5230011A
公开(公告)日：1993-07-20
申请号：US782048
申请日：1991-10-24
IPC分类号： H04B1/26 , H03B23/00 , H03B28/00 , H03D1/22 , H03D3/00 , H03D5/00 , H03D7/00 , H04B1/30 , H04N5/44
CPC分类号： H04N5/44 , H03D3/007 , H03B2200/0092 , H03B23/00 , H03B28/00 , H03D1/2245 , H03D2200/005 , H03D2200/0054 , H03D3/006 , H03D5/00 , H03D7/00
摘要： Receiver having an A/D converter for digitally sampling an analog signal modulated on a carrier frequency at a first sampling frequency, consecutively coupled to a digital quadrature mixer stage for a carrier frequency shift of the digitized modulated signal from the A/D converter, a digital filter device for selecting the phase quadrature signals of the quadrature mixer stage and for decimating the sampling frequency from the first sampling frequency to a second sampling frequency, and a digital demodulation device. To obtain a receiver which can be easily realized in an integrated form and for which less crystal surface is required than for the digital integrable receivers hitherto known, and which is particularly suitable for receiving RF radio or TV broadcast signals, the digital quadrature mixer stage includes comprises a first coordinate rotation digital computer (Cordic) in the rotation mode, having at least a first signal input which is coupled to an output of the A/D converter and a phase signal input to which a periodical digital sawtooth-shaped phase signal is applied from a digital sawtooth generator for a periodical 2.pi. phase rotation of at least the signal applied to the computer via the first signal input at a repetition frequency which is equal to the magnitude of the carrier frequency shift.
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公开(公告)号：US4393273A
公开(公告)日：1983-07-12
申请号：US226561
申请日：1981-01-19
CPC分类号： H04L7/0337 , H04H20/34 , H04H40/18 , H04L7/033
摘要： An FM-receiver with transmitter characterization, having a tuning unit, an IF-amplifier, a demodulation circuit for demodulating a discrete transmitter characterization signal, a clock regeneration circuit, a decoding device for decoding the discrete transmitter characterization signal and a signal processing unit. The clock regeneration circuit regenerates a clock signal the period of which is obtained by dividing the frequency of the stereo pilot signal. Synchronization of the clock signal phase with the phase of the clock signal used in the transmitter is carried out by detecting, using of a periodic window signal, the average phase of the code edges in the discrete transmitter characterization signal and by choosing the phase of the regenerated clock signal to be equal thereto.
摘要翻译： 具有发射机表征的FM接收机，具有调谐单元，IF放大器，用于解调离散发射机表征信号的解调电路，时钟再生电路，用于解码离散发射机表征信号的解码装置和信号处理单元。 时钟再生电路通过对立体声导频信号的频率进行分频而获得周期的时钟信号。 时钟信号相位与发射机中使用的时钟信号的相位的同步通过使用周期性窗口信号来检测离散发射机表征信号中的码边缘的平均相位并通过选择相位 再生时钟信号等于其。
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6.发明授权Receiver with quadrature decimation stage, method of processing digital signals 失效具有正交抽取级的接收机，数字信号处理方法
公开(公告)号：US5784414A
公开(公告)日：1998-07-21
申请号：US523704
申请日：1995-09-05
CPC分类号： H03D3/007 , H03D2200/005 , H03D2200/0056 , H03D3/006
摘要： In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).
摘要翻译： 在接收机中，接收信号以较高的采样频率被数字化（5）。 模拟滤波器（2,4）可以防止混叠。 数字化接收信号通过分路器（100）施加到正交数字信号处理器（9,10,11,12）。 在该处理器中，选择并解调所需的载波。 分离器（100）根据第一和第二变换函数（H1，H2）转换数字化的接收信号，以分别获得同相和正交分量（xi，yi）。 分路器中的采样频率减小（130,140）。 变换函数（H1，H2）的相位和幅度之间的具体关系可以防止混叠。 这种关系可以用相对简单的数字滤波器（110,120）来实现。
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公开(公告)号：US4884230A
公开(公告)日：1989-11-28
申请号：US209448
申请日：1988-05-04
IPC分类号： H03H17/02
CPC分类号： H03H17/0285
摘要： A digital lattice filter, comprising a plurality of identical stages each having a pair of inputs for receiving input signals and a pair of outputs for supplying output signals, these stages being connected in a cascade arrangement, each stage consisting in two mutually linked branches and no less than one of these branches comprising delay means, and in that always an even number of successive cascaded filter stages forms a group, in which both branches of each group of filter stages comprise a delay elements such that the time delay in the first branch is equal to the time delay in the second branch.
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8.发明授权
公开(公告)号：US4538285A
公开(公告)日：1985-08-27
申请号：US472375
申请日：1983-03-03
摘要： FM-receiver for receiving an FM-signal with transmission identification. An aerial input is connected to a tuning unit (1) to which there are connected, in succession, an IF-unit (2), an FM-detection circuit (3), a pilot regeneration circuit (10) for regenerating a pilot, a demodulation arrangement (12) for demodulating the code signal which contains transmission identification information, and a clock regeneration circuit (18) which is connected to both the pilot regeneration circuit (10) and the demodulation arrangement (12). The clock regeneration circuit comprises a resettable phase search circuit (18') for producing a clock signal whose frequency is derived from the regenerated pilot and whose phase is derived from the demodulated code signal, a clock-controlled decoding circuit (13) for decoding the code signal and a clock-controlled signal processing unit (17). For the purpose of stabilizing the processing, for example, for the reproduction of the transmission identification information, more specifically with mobile reception, use is made, in the event of disturbances of the code signal, of correctly decoded bits which were stored during undisturbed reception in a memory circuit ( 15). Only in the event of extreme interferences the phase search circuit (18') of the clock regeneration circuit (18) and also the other clock-controlled circuits (13-17) are reset to correct a possible phase slip of the clock signal.
摘要翻译： 用于接收具有传输标识的FM信号的FM接收机。 空中输入连接到连接有IF单元（2），FM检测电路（3），用于再生导频的导频再生电路（10）的调谐单元（1） 用于解调包含发送识别信息的码信号的解调装置（12）和连接到导频再生电路（10）和解调装置（12）的时钟再生电路（18）。 时钟再生电路包括一个可复位相位搜索电路（18'），用于产生一个时钟信号，该时钟信号的频率是从再生的导频导出的，并且相位是从解调的码信号得到的;时钟控制的解码电路（13） 代码信号和时钟控制信号处理单元（17）。 为了稳定处理的目的，例如，为了再现传输标识信息，更具体地说，对于移动接收，在代码信号的干扰的情况下，使用在不受干扰的接收期间存储的正确解码的位的使用 在存储器电路（15）中。 只有在极度干扰的情况下，时钟再生电路（18）的相位搜索电路（18'）以及其它时钟控制电路（13-17）被复位以校正时钟信号的可能的相移。
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