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公开(公告)号：US08198945B2
公开(公告)日：2012-06-12
申请号：US11917128
申请日：2006-05-30
IPC分类号： H03B27/00
CPC分类号： H03B27/00
摘要： The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.
摘要翻译： 本发明涉及振荡器电路和控制同相信号和正交信号的振荡频率的方法。 提供具有第一差分振荡器电路和第一差分耦合电路的第一振荡器装置（2），用于产生正交信号。 此外，提供具有第二差分振荡器电路和第二差分耦合电路的第二振荡器装置（4），用于产生同相信号。 提供频率控制装置，用于通过控制第一和第二振荡器装置的共模电流和尾电流中的至少一个来改变同相信号和正交信号的振荡频率。 由此，得到高线性的高频IQ振荡器。
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公开(公告)号：US08106720B2
公开(公告)日：2012-01-31
申请号：US12093704
申请日：2006-11-01
CPC分类号： H03C5/00
摘要： The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry. A bias input of the differential power amplifier circuitry is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry. Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.
摘要翻译： 本发明涉及极化调制装置和方法，其中基于输入信号的分别处理的相位调制（PM）和调幅（AM）分量产生极调调制信号。 通过使用差分功率放大器电路，根据相位调制和幅度调制分量产生放大的极化调制输出信号，并将放大的相位调制分量提供给差分功率放大器电路的差分输入。 基于幅度调制分量来控制差分功率放大器电路的偏置输入，以便调制差分功率放大器电路的共模电流。 因此，可以实现具有静态DC-DC转换器和功率和/或效率和/或线性控制的输出功率放大器的极性调制器的新概念。
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公开(公告)号：US07821342B2
公开(公告)日：2010-10-26
申请号：US11994783
申请日：2006-07-03
IPC分类号： H03F3/04
CPC分类号： H03F3/45 , H03F2200/372
摘要： Devices (1,2) comprising feedback-less amplifiers (16,19,26,29) that are gain controlled introduce linear relationships between output signals and input signals of the feedback-less amplifiers (16,19,26,29) by providing the feedback-less amplifiers (16,19,26,29) sub-circuits in the form of first transistors (33) operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors (34) for receiving control signals and third sub-circuits in the form of resistors (35) for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits (4) receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits (4) comprise current sources (6) and third and fourth transistors (41,42). The current sources (6) comprise fifth and sixth transistors (61,62). The second circuits (4) further comprise voltage sources (9) further current sources. Third circuits (8) compensate common mode currents.
摘要翻译： 包括无增益控制放大器（16,19,26,29）的设备（1,2），其被增益控制通过提供无反馈放大器（16,19,26,29）的输出信号和输入信号之间的线性关系来引入 在第三晶体管（33）的形式的无反馈放大器（16,19,26,29）子电路在其三极管区域中工作以接收输入信号，第二晶体管（34）形式的第二子电路用于 以电阻器（35）的形式接收控制信号和第三子电路，用于产生输出信号，由此相应的第一和第二和第三子电路形成串行路径。 第二电路（4）接收增益信号并将增益信号转换成控制信号。 控制信号是增益信号的副本。 第二电路（4）包括电流源（6）和第三和第四晶体管（41,42）。 电流源（6）包括第五和第六晶体管（61,62）。 第二电路（4）还包括电压源（9）的另外的电流源。 第三回路（8）补偿共模电流。
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公开(公告)号：US20080252381A1
公开(公告)日：2008-10-16
申请号：US11720319
申请日：2005-11-24
IPC分类号： H03F3/04
CPC分类号： H03F1/3211 , H03F1/22 , H03F3/19 , H03F3/30 , H03F3/343 , H03F3/345 , H03F3/45 , H03F2200/06 , H03F2200/294 , H03F2200/372 , H03F2200/513
摘要： A BALUN circuit (20) for low voltage operation for receiving single ended input signal at an input terminal (24) and providing a differential output signal across a pair of output terminals (OUT+, OUT−) is disclosed. The BALUN circuit (20) comprises a first branch including an input terminal (24) for receiving a single ended input voltage signal (RFin), a transistor (Q1), a resistance (R1) (28), a resistance (RL), and an output terminal (OUT+). A second branch includes a transistor (Q3), a resistance (RL) and an output terminal (OUT−). An operational amplifier (26) maintains current flowing through the resistances RL in the first and second branches substantially equal to each other, in dependence upon the output voltage signal across the output terminals (OUT+, OUT−).
摘要翻译： 公开了一种用于在输入端子（24）处接收单端输入信号并且在一对输出端子（OUT +，OUT-）之间提供差分输出信号的用于低电压操作的BALUN电路（20）。 BALUN电路（20）包括第一分支，其包括用于接收单端输入电压信号（RFin）的输入端子（24），晶体管（Q1），电阻（R 1）（28），电阻（RL ）和输出端子（OUT +）。 第二分支包括晶体管（Q 3），电阻（RL）和输出端（OUT-）。 运算放大器（26）根据输出端（OUT +，OUT-）两端的输出电压信号，保持流经第一和第二分支中的电阻RL的电流基本相等。
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公开(公告)号：US5994966A
公开(公告)日：1999-11-30
申请号：US17917
申请日：1998-02-03
申请人： Eduard F. Stikvoort
发明人： Eduard F. Stikvoort
CPC分类号： H03H11/04
摘要： A tunable balanced RC filter circuit of the type in which the resistors are formed as MOS transistors with variable gate voltages for tuning the filter. The MOS transistor takes the form of a series arrangement of individual MOS transistors (T1-1, T1-2, . . . , T1-N; T2-1, T2-2, . . . , T2-N) each having the same d.c. bias on its gate. The gate of each of the individual MOS transistors in the series arrangement also receives a fraction of the a.c. component of the input signal on the input terminals (IT1, IT2) of the two-port network by means of a resistor ladder (R1-1, R1-2, . . . , R1-N, R2-1, R2-2, . . . , R2-N), which is connected to the input terminals (IT1, IT2) via buffers (B1, B2). The a.c. component of the input signal is thus divided among the individual transistors in the series arrangement. In this way it is possible to use MOS transistors with a small gate voltage swing at comparatively large input voltages.
摘要翻译： 一种可调平衡RC滤波器电路，其中电阻器形成为具有可变栅极电压的MOS晶体管，用于调谐滤波器。 MOS晶体管采取单独的MOS晶体管（T1-1，T1-2，...，T1-N; T2-1，T2-2，...，T2-N）的串联布置的形式， 相同的直流 偏向门。 串联装置中的每个单独的MOS晶体管的栅极也接收一部分交流电。 通过电阻梯（R1-1，R1-2，...，R1-N，R2-1，R2-2）在双端口网络的输入端（IT1，IT2）上输入信号的分量 ，...，R2-N），其经由缓冲器（B1，B2）连接到输入端子（IT1，IT2）。 a.c. 输入信号的分量因此在串联装置中的各个晶体管之间分配。 以这种方式，可以在较大的输入电压下使用具有较小栅极电压摆幅的MOS晶体管。
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公开(公告)号：US4562591A
公开(公告)日：1985-12-31
申请号：US576588
申请日：1984-02-02
申请人： Eduard F. Stikvoort
发明人： Eduard F. Stikvoort
CPC分类号： H03G7/007
摘要： A digital dynamic range converter of the forward control type for varying the dynamic range of a digital audio signal constituted by a sequence of audio signal samples. Each audio signal sample x(n) is multiplied by a control signal sample s(n) which is delivered by a digital control signal generator. This control signal generator has applied to it unipolar signal samples x(n) which are derived via a transmission channel from the audio signal samples x(n). In order to cause this dynamic range converter to respond rapidly to abrupt variations in the audio signal and to render it moreover universally usable, the control signal generator is provided with a digital peak-value detector which converts the sequence of unipolar signal samples x(n) into a sequence of peak-value samples x(n). The latter are applied to a digital non-linear amplitude transformation circuit which has an adjustable amplitude transmission characteristic curve determined by adjustment quantities R and a. It delivers the transformation samples s(n) which are preferably converted in a digital low-pass filter into the control signal samples s(n) which are applied to the multiplier device.
摘要翻译： 一种用于改变由音频信号样本序列构成的数字音频信号的动态范围的正向控制类型的数字动态范围转换器。 每个音频信号样本x（n）乘以由数字控制信号发生器传送的控制信号采样s（n）。 该控制信号发生器已经向其应用了从音频信号样本x（n）经由传输信道导出的单极性信号样本x（n）。 为了使该动态范围转换器快速响应音频信号的突然变化并且使其更普遍地可用，控制信号发生器设置有数字峰值检测器，其将单极性信号样本序列x（n ）转换成峰值样本序列x（n）。 后者适用于数字非线性幅度变换电路，该电路具有由调节量R和a确定的可调幅度传输特性曲线。 它将优选地以数字低通滤波器转换的变换样本s（n）传送到施加到乘法器装置的控制信号样本s（n）。
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公开(公告)号：US20100219896A1
公开(公告)日：2010-09-02
申请号：US11917128
申请日：2006-05-30
IPC分类号： H03B5/12
CPC分类号： H03B27/00
摘要： The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.
摘要翻译： 本发明涉及振荡器电路和控制同相信号和正交信号的振荡频率的方法。 提供具有第一差分振荡器电路和第一差分耦合电路的第一振荡器装置（2），用于产生正交信号。 此外，提供具有第二差分振荡器电路和第二差分耦合电路的第二振荡器装置（4），用于产生同相信号。 提供频率控制装置，用于通过控制第一和第二振荡器装置的共模电流和尾电流中的至少一个来改变同相信号和正交信号的振荡频率。 由此，得到高线性的高频IQ振荡器。
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公开(公告)号：US07768322B2
公开(公告)日：2010-08-03
申请号：US11577182
申请日：2005-09-30
IPC分类号： H03K3/00
CPC分类号： H03F1/02 , H03F3/217 , H03F3/30 , H03F3/45089 , H03F2203/45248 , H03F2203/45366 , H03K17/16
摘要： The present invention provides a driving circuit (100) in particular for driving a laser diode (700) or a modulator, at data speed in the order of Gb/s. The driving circuit (10) has a low-voltage, high-speed output stage capable of driving efficiently a laser diode (700) or a modulator The driver circuit (10) comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (200, 201, 202), a push/pull stage (300), and an output stage (400) for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.
摘要翻译： 本发明提供一种驱动电路（100），特别是以Gb / s的数量速度驱动激光二极管（700）或调制器。 驱动电路（10）具有能够有效驱动激光二极管（700）或调制器的低电压，高速输出级。驱动电路（10）包括电路链，所述链包括压摆率控制 电路，至少一个跨线性放大器（200,201,202），推挽平台（300）和用于驱动负载电流的输出级（400）。 由于其多功能性，驾驶员可以用于其他应用，例如 线驱动器，电缆驱动器，用于背板互连的高速串行接口等。驱动器可以在低电源电压下工作，例如， 3.3V标称低至2.7V，具有高功率效率。 一个主要线索是完全使用由输出级产生的大信号电流，例如， 在驱动激光二极管中，不会浪费供电线路中的电流。
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9.发明授权Television receiver with saw filter coupling utilizing a series resonance network and additional resistor 失效具有锯齿式滤波器耦合的电视接收机，采用串联谐振网络和附加电阻
公开(公告)号：US5649313A
公开(公告)日：1997-07-15
申请号：US574799
申请日：1995-12-19
CPC分类号： H04N5/4446
摘要： In a television receiver a SAW filter (FSAW) is preceded by a coupling network (CNW). The coupling network (CNW) includes an inductor (LP) between two input terminals of the SAW filter (IS1, IS2). It further includes a series resonance circuit (SRC) coupled to at least one of the input terminals (IS1). In order to reduce signal distortion a resistor (RP) is coupled between the two input terminals (IS1, IS2). Alternatively, a resistor (RS) is coupled in parallel to the series resonance circuit (SRC).
摘要翻译： 在电视接收机中，SAW滤波器（FSAW）之前是耦合网络（CNW）。 耦合网络（CNW）包括在SAW滤波器（IS1，IS2）的两个输入端之间的电感器（LP）。 它还包括耦合到至少一个输入端子（IS1）的串联谐振电路（SRC）。 为了减少信号失真，电阻（RP）耦合在两个输入端（IS1，IS2）之间。 或者，电阻器（RS）与串联谐振电路（SRC）并联耦合。
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10.发明授权Interpolating filter arrangement with non-rational ratio between the input and the output sampling frequencies 失效插值滤波器布置在输入和输出采样频率之间具有非理性比
公开(公告)号：US4604720A
公开(公告)日：1986-08-05
申请号：US590096
申请日：1984-03-16
申请人： Eduard F. Stikvoort
发明人： Eduard F. Stikvoort
CPC分类号： H03H17/0642
摘要： Interpolating time-discrete filter arrangement for increasing the sampling frequency of a time-discrete signal from f.sub.i to f.sub.u, f.sub.u not being a rational multiple of f.sub.i. For the generation of the required filter coefficients this filter arrangement comprises clock pulse generators which produce input clock pulses ki(q) at a rate f.sub.i and output clock pulses ku(n) at a rate f.sub.u. It also comprises a coefficients generator in which a deviation component d(q) is calculated which indicates the relationship between the time interval T.sub.d(q) located between an input clock pulse k.sub.i (q) and the immediately preceding or the immediately subsequent output clock pulse ku(n) and the time interval T.sub.u =1/f.sub.u between two consecutive output clock pulses ku(n). In response to this deviation component the filter coefficients generator produces W filter coefficients, the w.sup.th filter coefficient (w=0, 1, 2, 3, . . . W-1) being equal to a(d(q),w) and being defined by the expressiona(d(q),w=h(d(q)T.sub.u +wT.sub.u)Herein the function h(v) represents the impulse response of a FIR filter and v a continuous variable in the interval -.infin.
摘要翻译： 插值时间离散滤波器布置，用于将时间离散信号的采样频率从fi增加到fu，而不是fi的合理倍数。 为了产生所需的滤波器系数，该滤波器装置包括时钟脉冲发生器，其以速率fi产生输入时钟脉冲ki（q），并以速率fu产生输出时钟脉冲ku（n）。 它还包括系数发生器，其中计算偏差分量d（q），其表示位于输入时钟脉冲ki（q）和紧接在前的或紧接着的输出时钟脉冲之间的时间间隔Td（q）之间的关系 ku（n）和两个连续输出时钟脉冲ku（n）之间的时间间隔Tu = 1 / fu。 响应于该偏差分量，滤波器系数发生器产生W个滤波器系数，第w个滤波器系数（w = 0,1,2,3，...，W-1）等于a（d（q），w）和 由（a）（d（q），w = h（d（q）Tu + wTu）表达式定义。这里，函数h（v）表示FIR滤波器的脉冲响应， <无限
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