Abstract:
A pseudo resistance circuit is disclosed that is capable of suppressing fluctuation in resistance value with fluctuation in process or temperature and facilitating adjustment. The pseudo resistance circuit includes a first MOSFET, a second MOSFET, a first current source which generates a first current substantially proportional to absolute temperature, and voltage source which generates a first voltage, which is a substantially linear function of absolute temperature. The gate of the first MOSFET and the gate of the second MOSFET are connected together, the second MOSFET is diode-connected, the first current is supplied to the drain of the second MOSFET, the first voltage is applied to the source of the second MOSFET, and a resistor having a resistance value according to the gate voltage of the first MOSFET is formed between the drain and the source of the first MOSFET.
Abstract:
An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.
Abstract:
A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
Abstract:
A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
Abstract:
A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.
Abstract:
A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.
Abstract:
An amplifier comprises an input terminal that inputs an AC voltage signal; an amplifying unit having a transistor for amplifying the input AC voltage signal; a current detecting unit connected internally of said amplifying unit; and a control-current source controlled by said current detecting unit that drives an input stage of the transistor.
Abstract:
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
Abstract:
A saturation detection and warning circuit having an adaptive threshold voltage is disclosed. The disclosed circuit can also be used to detect the impending drop out of the low drop out linear voltage regulator. A clamp circuit that clamps the amplifier's output voltage at a voltage that is separated from the adaptive threshold of the saturation detector and warning circuit by a controlled offset voltage is also disclosed.
Abstract:
A small signal amplifier with a large signal output boost stage are connected between first and second supply rails. The small signal amplifier receives first and second input signals and provides an output signal at an output node which drives a load. Under small signal conditions, the output signal varies approximately linearly with the difference voltage. However, under large signal conditions, a rail-to-rail large signal output boost stage connected to the output node is arranged to drive the output node close to the first or second supply rail as needed to provide the current demanded by the load. The large signal output boost stage is off in small signal conditions, but comes on rapidly and transfers maximum charge to the load under large signal conditions.