Invention Grant
US5784414A Receiver with quadrature decimation stage, method of processing digital
signals
失效
具有正交抽取级的接收机,数字信号处理方法
- Patent Title: Receiver with quadrature decimation stage, method of processing digital signals
- Patent Title (中): 具有正交抽取级的接收机,数字信号处理方法
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Application No.: US523704Application Date: 1995-09-05
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Publication No.: US5784414APublication Date: 1998-07-21
- Inventor: Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
- Applicant: Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
- Applicant Address: NY New York
- Assignee: U.S. Philips Corporation
- Current Assignee: U.S. Philips Corporation
- Current Assignee Address: NY New York
- Priority: EPX94202518 19940902
- Main IPC: H04L27/22
- IPC: H04L27/22 ; H03D3/00 ; H04B1/26 ; H04L27/14
Abstract:
In a the receiver, a reception signal is digitized (5) with a relatively high sampling frequency. Analog filters (2, 4) prevent aliasing. The digitized reception signal is applied via a splitter (100) to a quadrature digital signal processor (9, 10, 11, 12). In this processor, a desired carrier is selected and demodulated. The splitter (100) transforms the digitized reception signal in accordance with a first and a second transform function (H.sub.1, H.sub.2) to obtain in-phase and quadrature components (xi, yi), respectively. The sampling frequency is reduced (130, 140) in the splitter. A specific relation between the phase and magnitude of the transform functions (H.sub.1, H.sub.2) prevents aliasing. Such a relation can be achieved with relatively simple digital filters (110, 120).
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