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    Piezoelectric transformer
    4.
    发明授权
    Piezoelectric transformer 有权

    公开(公告)号：US09847472B2

    公开(公告)日：2017-12-19

    申请号：US14638168

    申请日：2015-03-04

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiroshi Asano

    IPC: H01L41/107 ,  H01L41/047

    CPC classification number: H01L41/107 ,  H01L41/0472

    Abstract: A piezoelectric transformer that includes a piezoelectric body having driving portions and a power generating portion, an input electrode, and an output electrode. The driving portions and the power generating portion are arranged in the lengthwise direction of the piezoelectric body. The driving portions are disposed symmetrically relative to a plane that passes through a center of the piezoelectric body in the lengthwise direction and is orthogonal to the lengthwise direction, occupy no less than half of the regions in the piezoelectric body, and are include two or more adjacent polarized regions.

    Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers
    8.
    发明授权
    Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers 有权
    低压晶体管和具有多个堆叠压电层的逻辑器件

    公开(公告)号：US09590167B2

    公开(公告)日：2017-03-07

    申请号：US15248488

    申请日：2016-08-26

    Applicant: International Business Machines Corporation

    Inventor： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

    IPC: H01L41/107 ,  H01L41/083 ,  H01L41/047 ,  H01L41/187

    CPC classification number: H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

    Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

    Abstract translation: 压电电子晶体管器件包括以堆叠配置布置的第一压电（PE）层，第二PE层和压阻（PR）层，其中PR层的电阻取决于施加的电压跨越第一和第二 PE层通过施加的压力由第一和第二PE层施加到PR层。 压电电子逻辑器件包括第一和第二压电晶体管（PET），其中第一PET的第一和第二PE层具有比第二PET的横截面积小的横截面面积，使得跨越第二PET层的PE层的电压降 第一PET在第一PET的PR层中产生小于由第二PET的PE层上的相同电压降产生的第二PET的PR层中的第二压力的第一压力。

    DC-AC POWER CONVERTING CIRCUIT
    9.
    发明申请
    DC-AC POWER CONVERTING CIRCUIT 审中-公开
    直流交流电源转换电路

    公开(公告)号：US20170012556A1

    公开(公告)日：2017-01-12

    申请号：US15016586

    申请日：2016-02-05

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： In Wha JEONG ,  Jae Suk SUNG ,  Hugh KIM

    IPC: H02M7/5387 ,  H01L41/107

    CPC classification number: H02M7/5387 ,  H01L41/044 ,  H01L41/107 ,  H02M3/337 ,  H02M5/10 ,  H02M2001/0077 ,  H02M2007/4815 ,  Y02B70/1433 ,  Y02B70/1441

    Abstract: A direct current (DC)-alternating current (AC) power convertor is disclosed. The DC-AC power converting circuit may include an inverter configured to convert the DC power into first output power, a piezoelectric transforming unit including piezoelectric transformers connected in parallel to an output terminal of the inverter, and each piezoelectric transformer of the piezoelectric transformers configured to transform the first output power to second output power, and an output configured to add the second output power output from the each of the piezoelectric transformer and to output AC power, wherein each piezoelectric transformer has a resonance frequency.

    Abstract translation: 公开了一种直流（DC）电流（AC）功率转换器。 DC-AC电力转换电路可以包括将DC电力转换为第一输出电力的逆变器，包括并联连接到逆变器的输出端子的压电变压器的压电变换单元，以及压电变压器的每个压电变压器，被配置为 将第一输出功率转换为第二输出功率，以及输出，被配置为将从压电变压器中的每一个输出的第二输出功率相加并输出AC电力，其中每个压电变压器具有谐振频率。

    LOW VOLTAGE TRANSISTOR AND LOGIC DEVICES WITH MULTIPLE, STACKED PIEZOELECTRONIC LAYERS
    10.
    发明申请
    LOW VOLTAGE TRANSISTOR AND LOGIC DEVICES WITH MULTIPLE, STACKED PIEZOELECTRONIC LAYERS 有权
    低电压晶体管和具有多个堆叠的电子层的逻辑器件

    公开(公告)号：US20160359099A1

    公开(公告)日：2016-12-08

    申请号：US15248488

    申请日：2016-08-26

    Applicant: International Business Machines Corporation

    Inventor： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

    IPC: H01L41/107 ,  H01L41/047 ,  H01L41/187 ,  H01L41/083

    CPC classification number: H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

    Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

    Abstract translation: 压电电子晶体管器件包括以堆叠配置布置的第一压电（PE）层，第二PE层和压阻（PR）层，其中PR层的电阻取决于施加的电压跨越第一和第二 PE层通过施加的压力由第一和第二PE层施加到PR层。 压电电子逻辑器件包括第一和第二压电晶体管（PET），其中第一PET的第一和第二PE层具有比第二PET的横截面积小的横截面面积，使得跨越第二PET层的PE层的电压降 第一PET在第一PET的PR层中产生小于由第二PET的PE层上的相同电压降产生的第二PET的PR层中的第二压力的第一压力。

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