公开(公告)号：US20240079375A1

公开(公告)日：2024-03-07

申请号：US18359020

申请日：2023-07-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroaki HOKAZONO

IPC: H01L23/00

CPC classification number: H01L24/745 ,  H01L24/85 ,  H01L2224/78343 ,  H01L2224/858

Abstract: A bonding tool for bonding two conductive plates in contact with each other by pressing the bonding tool against the two conductive plates while vibrating a bonding end portion thereof in a direction parallel to the conductive plates. The bonding end portion of the bonding tool includes a bonding base having an end surface, the end surface having a protrusion area that has two sides facing and parallel to each other in a first direction that is parallel to the end surface, a plurality of protrusions provided in the protrusion area of the end surface, and a suppression portion provided on the end surface along the two sides of the protrusion area. The bonding end portion is configured to vibrate in the first direction.

公开(公告)号：US09754927B2

公开(公告)日：2017-09-05

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L29/15 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

公开(公告)号：US08814054B2

公开(公告)日：2014-08-26

申请号：US13703255

申请日：2011-06-23

Applicant: Jean Brun ,  Laurent Lancon ,  Dominique Vicard

Inventor： Jean Brun ,  Laurent Lancon ,  Dominique Vicard

IPC: G06K19/06 ,  D02G3/36 ,  G06K19/077 ,  H01L25/00 ,  H01L23/00

CPC classification number: G06K19/07749 ,  D02G3/362 ,  D10B2401/18 ,  G06K19/07718 ,  G06K19/07758 ,  G06K19/07786 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/78 ,  H01L2224/8517 ,  H01L2224/858 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01058 ,  Y10T29/49002 ,  H01L2224/48 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method for forming a sheathed wire includes the steps of: axially advancing a core through a sheathing zone; wrapping a sheathing fiber around the core in the sheathing zone; and providing, in the sheathing zone, a series of microelectronic chip elements each provided with a wire section, in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire incorporating spaced-apart chip elements.

Abstract translation: 一种用于形成护套线的方法包括以下步骤：使芯通过护套区域轴向推进; 在护套区域围绕芯部缠绕护套纤维; 并且在护套区域中提供一系列各自设置有线部分的微电子芯片元件，使得围绕芯部包覆的护套纤维也缠绕在芯片元件及其线部分上以形成护套线 结合间隔开的芯片元件。

公开(公告)号：US09093289B2

公开(公告)日：2015-07-28

申请号：US13521589

申请日：2011-02-02

Applicant: Dominique Vicard ,  Jean Brun

Inventor： Dominique Vicard ,  Jean Brun

IPC: H05K7/06 ,  F21V21/00 ,  H05K13/00 ,  H01L29/06 ,  D03D1/00 ,  D03D9/00 ,  D03D15/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L29/0657 ,  D03D1/0088 ,  D03D9/00 ,  D03D15/00 ,  D10B2401/16 ,  D10B2401/18 ,  D10B2501/00 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/4807 ,  H01L2224/49 ,  H01L2224/858 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  Y10T29/49002 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

Abstract translation: 一种用于在两个基本上平行的拉紧螺纹上组装装置的方法。 该装置包括电子芯片和在装置的相对侧上开放的两个基本上平行的凹槽。 分离槽的距离对应于分开螺纹的距离。 该装置沿着垂直于凹槽平面的轴线具有穿透形状，在凹槽的水平处具有基部，并且具有比分开螺纹的距离更小的顶点。 该方法包括将装置的顶点放置在两个螺纹之间的步骤; 在所述两个螺纹之间移动所述装置，导致所述螺纹通过所述装置的穿透形状彼此分离; 并且在设备的持续运动中，直到螺纹穿透到凹槽中，从而恢复到其初始间隔距离。

公开(公告)号：US20140248747A1

公开(公告)日：2014-09-04

申请号：US14273785

申请日：2014-05-09

Applicant: Semiconductor Components Industries, LLC

Inventor： Atapol Prajuckamol ,  Bih Wen Fon ,  Jun Keat Lee

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49506 ,  H01L23/49541 ,  H01L23/49579 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/858 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract translation: 在一个实施例中，引线封装结构包括具有相对主表面的电子芯片。 电子芯片的一个主表面附接到第一和第二引线。 一个主表面电连接到第一引线，并与第二引线电隔离。 有源器件形成的另一个主表面可以电连接到第二引线。

公开(公告)号：US20130292856A1

公开(公告)日：2013-11-07

申请号：US13885257

申请日：2011-11-22

Applicant: Stefan Braun ,  Frank Niklaus ,  Andreas Fischer ,  Henrik Gradin

Inventor： Stefan Braun ,  Frank Niklaus ,  Andreas Fischer ,  Henrik Gradin

IPC: H01L23/00

CPC classification number: H01L24/85 ,  B23K20/007 ,  C22C19/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/94 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/45 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45155 ,  H01L2224/4813 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85099 ,  H01L2224/85205 ,  H01L2224/85345 ,  H01L2224/85375 ,  H01L2224/85385 ,  H01L2224/85399 ,  H01L2224/858 ,  H01L2224/85855 ,  H01L2224/85899 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01049 ,  H01L2924/00015 ,  H01L2924/20753 ,  H01L2924/01022

Abstract: The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Abstract translation: 本发明涉及一种将形状记忆合金线附着到基底上的方法，其中线被机械连接到基底上的3D结构中。 本发明还涉及一种装置，其包括附接到基底的形状记忆合金丝，其中线被机械地附接到基底上的3D结构中。

公开(公告)号：US20130234313A1

公开(公告)日：2013-09-12

申请号：US13414902

申请日：2012-03-08

Applicant: James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

Inventor： James Cooper Wainerdi ,  Luigi Colombo ,  John Paul Tellkamp ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/78 ,  H01L21/56 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: H01L23/373 ,  B82Y10/00 ,  C09J163/00 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32245 ,  H01L2224/331 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83862 ,  H01L2224/83897 ,  H01L2224/83951 ,  H01L2224/83986 ,  H01L2224/858 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2224/85899 ,  H01L2224/9205 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract translation: 一种制造方法包括在管芯（110）的第一侧上具有集成电路（105）的半导体管芯（110），在与第一侧相对的管芯（110）的第二侧上的扩散阻挡层（125） 基于所述扩散阻挡层（125）的碳纳米管（112）垫，与所述碳纳米管的所述垫（112）形成整体的芯片附接粘合剂（115）和粘附到所述模具 附着粘合剂和（115）和碳纳米管的垫（112），以经由碳纳米管（112）在管芯（110）和管芯焊盘（120）之间进行至少一些热转移。 还公开了其它制品，集成电路器件，结构以及制造工艺和组装工艺。

公开(公告)号：US09859236B2

公开(公告)日：2018-01-02

申请号：US14816648

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Meng Meng Chong ,  Xuesong Rao ,  Chim Seng Seet ,  Xiaohua Zhan

IPC: H01L23/00 ,  C22C9/01 ,  C22C9/05 ,  C22C9/00

CPC classification number: H01L24/05 ,  C22C9/00 ,  C22C9/01 ,  C22C9/05 ,  H01L24/03 ,  H01L24/85 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/858 ,  H01L2924/00014 ,  H01L2924/20752

Abstract: Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.

公开(公告)号：US20170040272A1

公开(公告)日：2017-02-09

申请号：US14816648

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Meng Meng Chong ,  Xuesong Rao ,  Chim Seng Seet ,  Xiaohua Zhan

IPC: H01L23/00 ,  C22C9/05 ,  C22C9/00 ,  C22C9/01

CPC classification number: H01L24/05 ,  C22C9/00 ,  C22C9/01 ,  C22C9/05 ,  H01L24/03 ,  H01L24/85 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/858 ,  H01L2924/00014 ,  H01L2924/20752

Abstract: Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.

Abstract translation: 提供具有氮化硅钝化层的铜结合结构的集成电路及其制造方法。 在示例性实施例中，集成电路包括具有接触表面的衬底和铜接合结构。 铜键合结构覆盖在衬底上。 由氮化硅形成的钝化层设置在接触表面上。

公开(公告)号：US20130092742A1

公开(公告)日：2013-04-18

申请号：US13703255

申请日：2011-06-23

Applicant: Jean Brun ,  Laurent Lancon ,  Dominique Vicard

Inventor： Jean Brun ,  Laurent Lancon ,  Dominique Vicard

IPC: G06K19/077

CPC classification number: G06K19/07749 ,  D02G3/362 ,  D10B2401/18 ,  G06K19/07718 ,  G06K19/07758 ,  G06K19/07786 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/78 ,  H01L2224/8517 ,  H01L2224/858 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01058 ,  Y10T29/49002 ,  H01L2224/48 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method for forming a sheathed wire includes the steps of axially advancing a core through a sheathing zone; wrapping a sheathing fiber around the core in the sheathing zone; and providing, in the sheathing zone, a series of microelectronic chip elements each provided with a wire section, in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire incorporating spaced-apart chip elements.

Abstract translation: 一种用于形成护套线的方法包括使芯通过护套区域轴向前进的步骤; 在护套区域围绕芯部缠绕护套纤维; 并且在护套区域中提供一系列各自设置有线部分的微电子芯片元件，使得围绕芯部包覆的护套纤维也缠绕在芯片元件及其线部分上以形成护套线 结合间隔开的芯片元件。