公开(公告)号：US20240055285A1

公开(公告)日：2024-02-15

申请号：US18494710

申请日：2023-10-25

Applicant: Lam Research Corporation

Inventor： Edward Augustyniak ,  David French ,  Sunil Kapoor ,  Yukinori Sakiyama ,  George Thomas

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/687

CPC classification number: H01L21/67288 ,  H01L21/67259 ,  H01L21/67253 ,  H01L21/67207 ,  H01L21/67069 ,  H01L21/67167 ,  H01J37/32183 ,  H01L21/68771 ,  H01J37/32385 ,  H01J37/32935 ,  H01J37/32577 ,  H01L21/67201 ,  H01J37/32715 ,  H01J2237/3321

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

公开(公告)号：US11756771B2

公开(公告)日：2023-09-12

申请号：US17162097

申请日：2021-01-29

Applicant: LAM RESEARCH CORPORATION

Inventor： Jack Chen ,  Adam Liron ,  Gregory Sexton

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01J37/32385 ,  H01J37/32091 ,  H01J37/32642 ,  H01L21/02087 ,  H01L21/67069 ,  Y10T29/49817

Abstract: A tunable upper plasma exclusion zone (PEZ) ring adjusts a distance of plasma during processing in a processing chamber and includes: a lower surface that includes: a horizontal portion; and an upwardly tapered outer portion that is conical and that extends outwardly and upwardly from the horizontal portion at an upward taper angle of about 5° to 50° with respect to the horizontal portion, where an outer diameter of the upwardly tapered outer portion is greater than 300 millimeters (mm), and where an inner diameter where the upwardly tapered outer portion begins to extend upwardly is less than 300 mm. A controller is to, during processing of a 300 mm circular substrate, adjust the distance of plasma for treatment of the 300 mm circular substrate at least one of radially inward and radially outward using the tunable upper PEZ ring.

公开(公告)号：US20180366305A1

公开(公告)日：2018-12-20

申请号：US16003954

申请日：2018-06-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi NAGAMI ,  Natsumi TORII

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32 ,  H01J37/32091 ,  H01J37/32385 ,  H01J37/32697 ,  H01J37/3299 ,  H01J2237/24564

Abstract: In a plasma processing apparatus, a controller controls one or both of a first high frequency power supply and a second high frequency power supply to periodically stop the supply of one or both of the first high frequency power and the second high frequency power. The controller also controls a switching unit to apply a DC voltage to a focus ring from a first time after a predetermined period of time in which a self-bias voltage of a lower electrode is decreased from a start point of each period in which one or both of the first high frequency power and the second high frequency power are supplied and to stop the application of the DC voltage to the focus ring during each period in which the supply of one or both of the first high frequency power and the second high frequency power is stopped.

公开(公告)号：US09564285B2

公开(公告)日：2017-02-07

申请号：US13942502

申请日：2013-07-15

Applicant: Lam Research Corporation

Inventor： Andreas Fischer ,  John Holland

IPC: H01J37/32 ,  H01J37/00

CPC classification number: H01J37/00 ,  H01J37/32091 ,  H01J37/32366 ,  H01J37/32385 ,  H01J37/32568 ,  H01J37/32642 ,  H01L2221/00

Abstract: A plasma processing system having at least a plasma processing chamber for performing plasma processing of a substrate and utilizing at least a first processing state and a second processing state. Plasma is present above the center region of the substrate during the first processing stale to perform plasma processing of at least the center region during the first processing state. Plasma is absent above the center region of the substrate but present adjacent to the bevel edge region during the second processing state to at least perform plasma processing of the bevel edge region during the second processing state. During the second processing state, the upper electrode is in an RF floating state and the substrate is disposed on the lower electrode surface.

Abstract translation: 一种等离子体处理系统，至少具有用于对基板进行等离子体处理并利用至少第一处理状态和第二处理状态的等离子体处理室。 在第一处理过程期间，等离子体存在于衬底的中心区域之上，以在第一处理状态期间至少执行中心区域的等离子体处理。 在第二处理状态期间，等离子体不存在于基板的中心区域上方，但在斜边缘区域附近存在，以至少在第二处理状态期间执行斜面边缘区域的等离子体处理。 在第二处理状态期间，上电极处于RF浮置状态，并且衬底设置在下电极表面上。

公开(公告)号：US09281166B2

公开(公告)日：2016-03-08

申请号：US14189978

申请日：2014-02-25

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Andrew D. Bailey, III

IPC: C23C16/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。

公开(公告)号：US20150099365A1

公开(公告)日：2015-04-09

申请号：US14046206

申请日：2013-10-04

Applicant: Lam Research Corporation

Inventor： Jack Chen ,  Adam Liron ,  Gregory Sexton

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/02087 ,  H01J37/32091 ,  H01J37/32385 ,  H01J37/32642 ,  H01L21/67069 ,  Y10T29/49817

Abstract: A bevel etcher for cleaning a bevel edge of a semiconductor substrate with plasma includes a lower electrode assembly having a lower support having a cylindrical top portion. An upper dielectric component is disposed above the lower electrode assembly having a cylindrical bottom portion opposing the top portion of the lower support. A tunable upper plasma exclusion zone (PEZ) ring surrounds the bottom portion of the dielectric component, wherein a lower surface of the tunable upper PEZ ring includes an upwardly tapered outer portion extending outwardly from the bottom portion of the upper dielectric component, wherein a vertical height of an adjustable gap between the lower surface of the upper PEZ ring and an upper surface of a substrate supported on the lower support can be increased or decreased such that the extent of the bevel edge of the substrate to be cleaned by the plasma can respectively be adjusted radially inward or radially outward. At least one radio frequency (RF) power source is adapted to energize process gas into the plasma during a bevel edge cleaning process.

Abstract translation: 用于用等离子体清洁半导体衬底的斜边缘的斜面蚀刻器包括具有具有圆柱形顶部的下支撑件的下电极组件。 上部电介质部件设置在下部电极组件的上方，该电极组件具有与下部支撑件的顶部相对的圆柱形底部。 可调谐上等离子体隔离区（PEZ）环围绕电介质部件的底部，其中可调谐上PEZ环的下表面包括从上介电部件的底部向外延伸的向上锥形的外部，其中垂直 可以增加或减少上PEZ环的下表面和支撑在下支撑件上的基底的上表面之间的可调节间隙的高度，使得待等离子体待清洁的基底的斜边的范围可分别 径向向内或径向向外调节。 至少一个射频（RF）电源适于在斜边清洁过程期间将处理气体激发到等离子体中。

公开(公告)号：US20140174661A1

公开(公告)日：2014-06-26

申请号：US14189978

申请日：2014-02-25

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Andrew D. Bailey, III

IPC: H01J37/32

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。

公开(公告)号：US20130233490A1

公开(公告)日：2013-09-12

申请号：US13870917

申请日：2013-04-25

Applicant: LAM RESEARCH CORPORATION

Inventor： Andrew D. Bailey, III ,  Yunsang Kim

IPC: H01L21/67

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。

公开(公告)号：US08100081B1

公开(公告)日：2012-01-24

申请号：US11515346

申请日：2006-08-31

Applicant: Jon Henri ,  Henner Meinhold ,  Christopher Gage ,  Dan Doble

Inventor： Jon Henri ,  Henner Meinhold ,  Christopher Gage ,  Dan Doble

IPC: C23C16/452 ,  C23C16/455 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

CPC classification number: H01L21/02087 ,  C23F4/00 ,  H01J37/32385 ,  H01J37/32449 ,  H01L21/31138 ,  H01L21/6708

Abstract: The present invention provides methods and apparatuses for removing unwanted film from the edge area of substrate using remotely-generated plasmas. Activated plasma species are directed to the edge of the substrate to contact and remove the unwanted film, while intrusion of the activated species to areas above the active circuit region (where the film is desired) is suppressed. In certain embodiments, intrusion of the activated species is suppressed by the use of a purge gas and/or the use of materials that promote recombination of plasma species. In particular embodiments, atomic oxygen is used to remove ashable films from the edge of semiconductor wafers.

Abstract translation: 本发明提供了使用远程产生的等离子体从衬底的边缘区域去除不想要的膜的方法和装置。 激活的等离子体物质被引导到基底的边缘以接触和去除不需要的膜，同时抑制活性物质侵入有源电路区域之上（其中需要膜）的区域。 在某些实施方案中，通过使用吹扫气体和/或促进等离子体物质重组的材料的使用来抑制活化物质的侵入。 在具体实施方案中，使用原子氧从半导体晶片的边缘去除可灰化膜。

公开(公告)号：US20240079199A1

公开(公告)日：2024-03-07

申请号：US18505522

申请日：2023-11-09

Applicant: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.

Inventor： Syuta Ochi

IPC: H01J37/08 ,  H01J37/063 ,  H01J37/317 ,  H01J37/32

CPC classification number: H01J37/08 ,  H01J37/063 ,  H01J37/3171 ,  H01J37/32385 ,  H01J37/32788 ,  H01J2237/082

Abstract: An ion generator includes an arc chamber defining a plasma generation space, and a cathode which emits thermoelectrons toward the plasma generation space. The arc chamber includes a box-shaped main body having an opening, and a slit member mounted to cover the opening and provided with a front slit. An inner surface of the main body is exposed to the plasma generation space made of a refractory metal material. The slit member includes an inner member made of graphite and an outer member made of another refractory metal material. The outer member includes an outer surface exposed to an outside of the arc chamber. The inner member includes an inner surface exposed to the plasma generation space, and an opening portion which forms the front slit extending from the inner surface of the inner member to the outer surface of the outer member.