公开(公告)号：US11768787B2

公开(公告)日：2023-09-26

申请号：US16256162

申请日：2019-01-24

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： Robert David Rand ,  Graeme Gordon Mackay ,  Andrew James Howlett

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F13/40

CPC分类号： G06F13/385 ,  G06F13/122 ,  G06F13/382 ,  G06F13/4022

摘要： This application relates to methods and apparatus for transfer of data between a host device (400) and a peripheral device (300) via a USB Type-C connector (100; 304) of the host device. A data controller is described that has a path controller (309, 310; 706) for establishing signal paths between circuitry of the host device and contacts (101) of said USB Type-C connector. The path controller is operable in at least first and second modes. In the first mode the path controller establishes separate signal paths to each of at least first, second, third and fourth contacts (A6, A7, B6, B7) of the USB Type-C connector and a plurality of the established signal paths are for transfer of analogue audio data. In the second mode the path controller establishes a pair of signal paths to only a subset of said first to fourth contacts to provide a differential digital data path.

公开(公告)号：US20230267089A1

公开(公告)日：2023-08-24

申请号：US18112740

申请日：2023-02-22

申请人： Google LLC

发明人： Santanu Dasgupta ,  Durgaprasad V. Ayyadevara ,  Bor Chan ,  Prashant R. Chandra ,  Bok Knun Randolph Chung ,  Max Kamenetsky ,  Rajeev Koodli ,  Shahin Valoth

IPC分类号： G06F13/38 ,  G06F13/12

CPC分类号： G06F13/385 ,  G06F13/122 ,  G06F2213/0038

摘要： The present disclosure provides a compute platform architecture for virtualized and cloud native network functions. The architecture uses a reduced instruction set computer-based general purpose processor along with multiple special purpose accelerators and an integrated network interface card. As such, the architecture can accommodate multiple hundreds of gigabits of input/output.

公开(公告)号：US11665474B1

公开(公告)日：2023-05-30

申请号：US17685019

申请日：2022-03-02

申请人： Dell Products L.P.

发明人： Padmanabhan Narayanan ,  Vamshidhar Varre

IPC分类号： H04R3/00 ,  H04R1/02 ,  H04R17/00 ,  G06F13/12

CPC分类号： H04R3/00 ,  G06F13/122 ,  H04R1/025 ,  H04R17/00

摘要： An audible beacon system includes an audible beacon chassis. A port connector is included on the audible beacon chassis and is configured to connect to a port on a computing device. An audible beacon device is coupled to the audible beacon chassis. An audible beacon driver device is included in the audible beacon chassis, is accessible via the port connector, and is configured to drive the audible beacon device to cause the audible beacon device to generate an audible sound. A storage device is included in the audible beacon chassis, is accessible via the port connector, and includes information that is configured to allow a computing device that is connected to the port connector to access the audible beacon driver device and cause the audible beacon driver device to drive the audible beacon device.

公开(公告)号：US20190196565A1

公开(公告)日：2019-06-27

申请号：US16229286

申请日：2018-12-21

申请人： BROTHER KOGYO KABUSHIKI KAISHA

发明人： Yasuhiro SHIMAMURA

IPC分类号： G06F1/3234 ,  G06F1/26 ,  G06F13/12 ,  H02J7/00

CPC分类号： G06F1/325 ,  G06F1/266 ,  G06F13/122 ,  G06F2213/0042 ,  H02J7/0052 ,  H02J2007/006 ,  H02J2007/0062

摘要： An information processing apparatus includes: an interface; a battery; and a controller. The controller is configured to: determine whether a reduction notification indicating reduction in the electric power is received from an external device when the interface is receiving the electric power of a first power amount from the external device; and request the external device via the interface to supply the electric power of a second power amount that is less than the first power amount and greater than or equal to an amount of the electric power consumed in self-discharge of the battery.

公开(公告)号：US20180336145A1

公开(公告)日：2018-11-22

申请号：US15974862

申请日：2018-05-09

申请人： MELEXIS TECHNOLOGIES NV

发明人： Philippe LAUGIER ,  Benoit HEROUX ,  Thomas FREITAG

IPC分类号： G06F13/12 ,  G06F11/10

CPC分类号： G06F13/126 ,  G06F9/30 ,  G06F11/08 ,  G06F11/10 ,  G06F11/106 ,  G06F11/1096 ,  G06F11/2043 ,  G06F13/122 ,  G06F15/7832

摘要： A method for performing an initialization or a reset of a port of an integrated circuit includes: receiving in a device for supervising ports, from a central processing unit of the integrated circuit, a port initialisation signal comprising port initialisation data and one or more parity bits; inverting in the device for supervising ports the one or more parity bits in accordance with the port initialization signal; providing the port initialisation signal comprising the port initialisation data and the inverted one or more parity bits to the port of the integrated circuit; on receipt of the port initialisation signal at the port, inverting again in the port the inverted one or more parity bits, thereby obtaining the original one or more parity bits and storing the port initialisation data and the just obtained original one or more parity bits.

公开(公告)号：US20180300281A1

公开(公告)日：2018-10-18

申请号：US15953866

申请日：2018-04-16

申请人： Valmet Automation Oy

发明人： Vesa Saastamoinen

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/42 ,  G06F13/122 ,  G06F13/4022 ,  G06F13/4068

摘要： The invention relates to an apparatus, a device and a method. The apparatus is configured for providing an address to a device attachable with the apparatus. The apparatus comprises at least one connector capable of receiving the device, an address composer for producing an address signal, and an address line in the connector for providing the address signal to the device, the address signal being indicative of an address to be used by the device when attached with the apparatus. The address composer is configured to generate the address signal as an analogue address signal. The device comprises at least one connector capable of receiving the device, an address composer for producing an address signal, an address line in the connector for providing the address signal to the device, the address signal being indicative of an address to be used by the device when attached with the apparatus, an input for receiving the address signal as an analogue address signal, a comparator for comparing the level of the analogue address signal with a set of reference values; and a determinator to determine the address to be used by the device on the basis of the comparison result.

公开(公告)号：US20180224885A1

公开(公告)日：2018-08-09

申请号：US15884802

申请日：2018-01-31

申请人： FUJITSU LIMITED

发明人： Joshua Liang ,  Ali Sheikholeslami ,  Yuuki Ogata ,  Hirotaka TAMURA

IPC分类号： G06F1/12 ,  H03K5/01 ,  H03K19/23 ,  H03L7/093 ,  G06F13/12 ,  H04L1/20

CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F13/122 ,  H03K5/01 ,  H03K19/23 ,  H03K2005/00058 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L1/205

摘要： A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.

公开(公告)号：US09952913B2

公开(公告)日：2018-04-24

申请号：US15412198

申请日：2017-01-23

申请人： Atmel Corporation

发明人： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC分类号： G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F9/52 ,  G06F13/28 ,  G06F13/42

CPC分类号： G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

摘要： Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

公开(公告)号：US20180099627A1

公开(公告)日：2018-04-12

申请号：US15724296

申请日：2017-10-04

申请人： Yazaki Corporation

发明人： Mihoko SOWA

IPC分类号： B60R16/02

CPC分类号： B60R16/02 ,  G06F13/122

摘要： A custom IC designed so as to control an operation of a predetermined output device includes one or more terminals for setting output device capable to set control information corresponding to the predetermined output device to be connected to an output terminal of the custom IC. A setting signal outputted from the terminals for setting output device is generated depending on the presence or absence of a connection between each of the terminals for setting output device and a ground potential through a conductive connecting member.

公开(公告)号：US09921987B2

公开(公告)日：2018-03-20

申请号：US15218727

申请日：2016-07-25

申请人： Intel Corporation

发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC分类号： G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16 ,  G11C29/52

CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.