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公开(公告)号：US11617034B2
公开(公告)日：2023-03-28
申请号：US17187898
申请日：2021-03-01
摘要： An integrated circuit for digital signal routing. Signal routing is achieved with a multiply-accumulate block, which takes data from one or more data sources and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock.
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公开(公告)号：US09490765B2
公开(公告)日：2016-11-08
申请号：US14864619
申请日：2015-09-24
CPC分类号： H04R3/00 , H03F3/183 , H03F2200/03 , H03G3/348 , H04R29/004 , H04R2420/03 , H04R2420/05
摘要： A host device for use with a removable peripheral apparatus having a microphone, and to the biasing circuitry for said microphone. The host device may have a device connector for forming a mating connection with a respective peripheral connector. A source of bias is arranged to supply an electrical bias to a device microphone contact of the device connector via a biasing path. A capacitor is connected between a reference voltage node and a capacitor node of the biasing path. A first switch is located between the capacitor node and the device microphone contact. Detection circuitry detects disconnection of the peripheral connector and device connector; and control circuitry controls the switch to disable the biasing path.
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公开(公告)号：US11438694B2
公开(公告)日：2022-09-06
申请号：US17187897
申请日：2021-03-01
摘要： An integrated circuit for digital signal routing. Signal routing is achieved with a multiply-accumulate block, which takes data from one or more data sources and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock.
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公开(公告)号：US10728654B2
公开(公告)日：2020-07-28
申请号：US16184199
申请日：2018-11-08
IPC分类号： H04B1/00 , G06F13/362 , H04B7/26 , H04J3/00 , H04L12/403 , H04J3/06 , H04R3/00 , H04H60/04 , H04R25/00 , H04B3/00 , H04R5/02
摘要： An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
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公开(公告)号：US20210185441A1
公开(公告)日：2021-06-17
申请号：US17187898
申请日：2021-03-01
摘要： An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
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公开(公告)号：US09661434B2
公开(公告)日：2017-05-23
申请号：US15342232
申请日：2016-11-03
IPC分类号： H04R29/00
CPC分类号： H04R3/00 , H03F3/183 , H03F2200/03 , H03G3/348 , H04R29/004 , H04R2420/03 , H04R2420/05
摘要： A host device for use with a removable peripheral apparatus having a microphone, and to the biasing circuitry for said microphone. The host device may have a device connector for forming a mating connection with a respective peripheral connector. A source of bias is arranged to supply an electrical bias to a device microphone contact of the device connector via a biasing path. A capacitor is connected between a reference voltage node and a capacitor node of the biasing path. A first switch is located between the capacitor node and the device microphone contact. Detection circuitry detects disconnection of the peripheral connector and device connector; and control circuitry controls the switch to disable the biasing path.
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公开(公告)号：US20180041833A1
公开(公告)日：2018-02-08
申请号：US15686968
申请日：2017-08-25
摘要： An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.1 kHz or 48 kHz.
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公开(公告)号：US09774951B2
公开(公告)日：2017-09-26
申请号：US14826891
申请日：2015-08-14
摘要： An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
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公开(公告)号：US20160056786A1
公开(公告)日：2016-02-25
申请号：US14864619
申请日：2015-09-24
CPC分类号： H04R3/00 , H03F3/183 , H03F2200/03 , H03G3/348 , H04R29/004 , H04R2420/03 , H04R2420/05
摘要： A host device for use with a removable peripheral apparatus having a microphone, and to the biasing circuitry for said microphone. The host device may have a device connector for forming a mating connection with a respective peripheral connector. A source of bias is arranged to supply an electrical bias to a device microphone contact of the device connector via a biasing path. A capacitor is connected between a reference voltage node and a capacitor node of the biasing path. A first switch is located between the capacitor node and the device microphone contact. Detection circuitry detects disconnection of the peripheral connector and device connector; and control circuitry controls the switch to disable the biasing path.
摘要翻译： 用于与具有麦克风的可移动外围设备一起使用的主机设备，以及用于所述麦克风的偏置电路。 主机设备可以具有用于与相应的外围连接器形成配合连接的设备连接器。 偏置源被布置成经由偏置路径向设备连接器的设备麦克风接触件提供电偏压。 电容器连接在参考电压节点和偏置路径的电容器节点之间。 第一个开关位于电容器节点和设备麦克风接点之间。 检测电路检测外围连接器和设备连接器的断开; 并且控制电路控制开关以禁用偏置路径。
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公开(公告)号：US20160044412A1
公开(公告)日：2016-02-11
申请号：US14826891
申请日：2015-08-14
摘要： An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
摘要翻译： 一种用于数字信号路由的集成电路。 集成电路具有模拟和数字输入和输出，包括用于连接到其他集成电路的数字接口。 输入，包括数字接口，作为数据源。 输出，包括数字接口，充当数据目的地。 该集成电路还包括可用作数据源和数据目的地的信号处理块。 信号路由通过乘法累加块实现，该乘法块从一个或多个数据源获取数据，并且在任何所需的缩放之后生成数据目的地的输出数据。 来自数据源的数据在数据采样时钟的整个周期中被缓冲，使得乘法累加块可以在该周期中的任何点检索数据，并且乘法累加块的输出数据被缓冲在整个周期 数据采样时钟，使得数据目的地可以在该周期的任何时间点检索数据。 多个信号路径可以由用户或软件提供给设备的配置数据来定义。 乘法累加块以时分复用为基础进行操作，从而可以在采样时钟的一个周期内处理多个信号路径。 每个信号路径具有各自的采样时钟速率，并且具有不同采样时钟速率的路径可以彼此独立地以时分复用为基础通过乘法累加块路由。 因此，可以以44Hz或48kHz的音频数据同时处理8kHz或16kHz的语音信号。
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