公开(公告)号：US10164880B2

公开(公告)日：2018-12-25

申请号：US14541472

申请日：2014-11-14

申请人： Intel Corporation

发明人： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Rohit R. Verma ,  Robert P. Adler

IPC分类号： H04L12/741 ,  H04L29/06 ,  G06F15/78 ,  G06F13/40

摘要： In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.

公开(公告)号：US09588922B2

公开(公告)日：2017-03-07

申请号：US14668013

申请日：2015-03-25

申请人： Intel Corporation

发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC分类号： G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

摘要翻译： 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US20160109925A1

公开(公告)日：2016-04-21

申请号：US14978340

申请日：2015-12-22

申请人： Intel Corporation

发明人： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

IPC分类号： G06F1/32

CPC分类号： G06F1/325 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

摘要： A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.

摘要翻译： 提供了一种芯片系统（SoC），包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。 根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测 电路被禁用，并且不保持共模电压。 根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

公开(公告)号：US20160085707A1

公开(公告)日：2016-03-24

申请号：US14801880

申请日：2015-07-17

申请人： Intel Corporation

发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

公开(公告)号：US09274987B2

公开(公告)日：2016-03-01

申请号：US14668028

申请日：2015-03-25

申请人： Intel Corporation

发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC分类号： G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

摘要翻译： 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US20150067412A1

公开(公告)日：2015-03-05

申请号：US14503637

申请日：2014-10-01

申请人： Intel Corporation

发明人： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Rohit R. Verma

IPC分类号： G06F11/07 ,  G06F13/42

CPC分类号： G06F11/0772 ,  G06F11/0784 ,  G06F11/0793 ,  G06F13/4221

摘要： In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种处理在根据使用PCI Express™语义的外围组件互连（PCI）规范设计的代理中接收到的请求的方法。 更具体地，响应于确定代理不支持请求，可以更新代理的不支持的请求检测注册器，以及从代理发送的指示代理不支持该请求的响应。 描述和要求保护其他实施例。

公开(公告)号：US20210389371A1

公开(公告)日：2021-12-16

申请号：US17461364

申请日：2021-08-30

申请人： Intel Corporation

发明人： Vui Yong Liew ,  Zhenyu Zhu ,  Mikal C. Hunsaker ,  Wai Mun Ng

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F13/16 ,  G06F13/42

摘要： An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.

公开(公告)号：US10229080B2

公开(公告)日：2019-03-12

申请号：US14801880

申请日：2015-07-17

申请人： Intel Corporation

发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

IPC分类号： G06F13/20 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

公开(公告)号：US10185385B2

公开(公告)日：2019-01-22

申请号：US15180466

申请日：2016-06-13

申请人： Intel Corporation

发明人： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

IPC分类号： G06F1/32

摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.

公开(公告)号：US20170024343A1

公开(公告)日：2017-01-26

申请号：US15218727

申请日：2016-07-25

申请人： Intel Corporation

发明人： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC分类号： G06F13/364 ,  G11C29/52 ,  G06F13/42 ,  G06F11/10 ,  G06F11/07

CPC分类号： G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

摘要： Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

摘要翻译： 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与另一个组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。