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    Dual bus standard switching bus controller
    2.
    发明授权
    Dual bus standard switching bus controller 有权
    双总线标准交换总线控制器

    公开(公告)号：US09098642B2

    公开(公告)日：2015-08-04

    申请号：US14194893

    申请日：2014-03-03

    申请人： Intel Corporation

    发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

    IPC分类号： G06F13/20 ,  G06F13/28 ,  G06F13/40 ,  G06F13/38

    CPC分类号： G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

    摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    摘要翻译： 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

    Virtualized link states of multiple protocol layer package interconnects
    3.
    发明授权
    Virtualized link states of multiple protocol layer package interconnects 有权

    公开(公告)号：US11663154B2

    公开(公告)日：2023-05-30

    申请号：US17721413

    申请日：2022-04-15

    申请人： Intel Corporation

    发明人： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    CPC分类号： G06F13/4031 ,  G06F13/1652 ,  G06F13/387 ,  G06F13/4208 ,  G06F13/4265

    摘要： Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

    Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle
    4.
    发明授权
    Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle 有权
    处理器通过激活根端口隐藏其上电延迟并快速发送下游周期

    公开(公告)号：US09563256B2

    公开(公告)日：2017-02-07

    申请号：US13734577

    申请日：2013-01-04

    申请人： Intel Corporation

    发明人： Sun Zheng E ,  Ting Lok Song ,  Poh Thiam Teoh ,  Jennifer Chin ,  Say Cheong Gan ,  Sujea Lim ,  Su Wei Lim

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

    摘要翻译： 本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。 在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。 另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。

    System, Apparatus And Method For Synchronizing Multiple Virtual Link States Over A Package Interconnect
    6.
    发明申请
    System, Apparatus And Method For Synchronizing Multiple Virtual Link States Over A Package Interconnect 有权

    公开(公告)号：US20230026906A1

    公开(公告)日：2023-01-26

    申请号：US17819390

    申请日：2022-08-12

    申请人： Intel Corporation

    发明人： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/42

    摘要： In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

    VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCONNECTS
    7.
    发明申请
    VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCONNECTS 有权

    公开(公告)号：US20220350769A1

    公开(公告)日：2022-11-03

    申请号：US17721413

    申请日：2022-04-15

    申请人： Intel Corporation

    发明人： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    摘要： Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

    Virtualized link states of multiple protocol layer package interconnects
    8.
    发明授权
    Virtualized link states of multiple protocol layer package interconnects 有权

    公开(公告)号：US11308018B2

    公开(公告)日：2022-04-19

    申请号：US17015963

    申请日：2020-09-09

    申请人： Intel Corporation

    发明人： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    摘要： Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

    VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCONNECTS
    9.
    发明申请
    VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCONNECTS 审中-公开

    公开(公告)号：US20190227972A1

    公开(公告)日：2019-07-25

    申请号：US16373472

    申请日：2019-04-02

    申请人： Intel Corporation

    发明人： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

    摘要： Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.