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    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE
    3.
    发明申请
    PROVIDING MULTIPLE ROOTS IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中提供多个引脚

    公开(公告)号：US20160357700A1

    公开(公告)日：2016-12-08

    申请号：US14880443

    申请日：2015-10-12

    Applicant: Intel Corporation

    Inventor： Michael T. Klinglesmith ,  Chang Yong Kang ,  Robert DeGruijl ,  Ioannis T. Schoinas ,  Darren Abramson ,  Khee Wooi Lee

    IPC: G06F13/42 ,  G06F12/08 ,  G06F13/16 ,  G06F3/06

    CPC classification number: G06F13/4282 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/068 ,  G06F12/0828 ,  G06F13/1663 ,  G06F2212/621

    Abstract: In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，系统包括：与第一根空间标识符相关联并包括至少一个第一主处理器和第一代理的第一根空间，所述至少一个第一主处理器和与第一根空间标识符相关联的第一代理 ; 与第二根空间标识符相关联并且包括至少一个第二主处理器和第二代理的第二根空间，所述至少一个第二主处理器和与所述第二根空间标识符相关联的第二代理; 以及共享结构，用于耦合第一根空间和第二根空间，共享结构至少部分地基于事务的根空间字段将事务路由到第一根空间或第二根空间。 描述和要求保护其他实施例。

    LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO A COHERENT FABRIC
    4.
    发明申请
    LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO A COHERENT FABRIC 审中-公开
    高速缓存代码对相邻纸张的低层叠层连接性

    公开(公告)号：US20160188469A1

    公开(公告)日：2016-06-30

    申请号：US14583611

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

    IPC: G06F12/08 ,  G06F13/42 ,  G06F13/28

    CPC classification number: G06F12/0815 ,  G06F9/5016 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/287 ,  G06F13/4282 ,  G06F2212/1028 ,  G06F2212/154 ,  G06F2212/621

    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

    Abstract translation: 在一个示例中，片上系统包括多个多核处理器，例如用于八个总核的四个双核处理器。 每个处理器通过共享的无孔结构连接到诸如存储器和外围设备之类的共享资源。 因为每个核心的每个输入总线可以包含数百条数据线，所以共享的非空心结构中的行数可能变得过高。 因此，来自每个核的输入被复用，例如以二对一的配置。 多路复用可以是非阻塞排队（例如FIFO）复用，以确保来自所有核心的所有分组被传送到非空心结构。 在某些实施例中，可以向未多路复用的非空心结构提供一些较小的输入线，并且还可以将从非织造结构返回（输出）到芯的非多路复用。

    GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC
    8.
    发明申请
    GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC 审中-公开
    系统级芯片中心质量保证质量保证

    公开(公告)号：US20160188529A1

    公开(公告)日：2016-06-30

    申请号：US14583142

    申请日：2014-12-25

    Applicant: Intel Corporation

    Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Marc Torrant ,  James A. Coleman ,  Peter J. Elardo ,  Eric A. Geisler

    IPC: G06F15/78 ,  G06F13/16 ,  G06F13/18 ,  G06F12/08

    CPC classification number: G06F15/7814 ,  G06F12/0811 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/18 ,  G06F15/781 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14

    Abstract: In an example, a control system may include a system-on-a-chip (SoC), including one processor for real-time operation to manage devices in the control system, and another processor configured to execute auxiliary functions such as a user interface for the control system. The first core and second core may share memory such as dynamic random access memory (DRAM), and may also share an uncore fabric configured to communicatively couple the processors to one or more peripheral devices. The first core may require a guaranteed quality of service (QoS) to memory and/or peripherals. The uncore fabric may be divided into a first “real-time” virtual channel designated for traffic from the first processor, and a second “auxiliary” virtual channel designated for traffic from the second processor. The uncore fabric may apply a suitable selection or weighting algorithm to the virtual channels to guarantee the QoS.

    Abstract translation: 在一个示例中，控制系统可以包括片上系统（SoC），其包括用于实时操作的一个处理器来管理控制系统中的设备，以及另一处理器，其被配置为执行辅助功能，例如用户接口 用于控制系统。 第一核心和第二核心可以共享诸如动态随机存取存储器（DRAM）的存储器，并且还可以共享被配置为将处理器通信地耦合到一个或多个外围设备的非空心结构。 第一个核心可能需要对存储器和/或外设的有保证的服务质量（QoS）。 非空心结构可以被划分为从第一处理器指定用于业务的第一“实时”虚拟通道和被指定用于来自第二处理器的业务的第二“辅助”虚拟通道。 不织布可以对虚拟信道应用合适的选择或加权算法来保证QoS。

    Providing Error Handling Support To Legacy Devices
    9.
    发明申请
    Providing Error Handling Support To Legacy Devices 审中-公开
    为旧设备提供错误处理支持

    公开(公告)号：US20150067412A1

    公开(公告)日：2015-03-05

    申请号：US14503637

    申请日：2014-10-01

    Applicant: Intel Corporation

    Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Rohit R. Verma

    IPC: G06F11/07 ,  G06F13/42

    CPC classification number: G06F11/0772 ,  G06F11/0784 ,  G06F11/0793 ,  G06F13/4221

    Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种处理在根据使用PCI Express™语义的外围组件互连（PCI）规范设计的代理中接收到的请求的方法。 更具体地，响应于确定代理不支持请求，可以更新代理的不支持的请求检测注册器，以及从代理发送的指示代理不支持该请求的响应。 描述和要求保护其他实施例。

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