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公开(公告)号:US10185385B2
公开(公告)日:2019-01-22
申请号:US15180466
申请日:2016-06-13
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号: G06F1/32
摘要: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
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公开(公告)号:US20170123475A1
公开(公告)日:2017-05-04
申请号:US15180466
申请日:2016-06-13
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号: G06F1/32
CPC分类号: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
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公开(公告)号:US10892914B2
公开(公告)日:2021-01-12
申请号:US16233395
申请日:2018-12-27
申请人: INTEL CORPORATION
发明人: Assaf Gurevitz , Oren Kaidar , Rafi Ben-Tal , Elad Meir , Hagay Barel
摘要: For example, a wireless communication receiver may be configured to switch one or more RF components of the receiver between an on-state and an off-state based on at least one detection criterion for preamble detection of a frame preamble by a preamble detector of the receiver, switching the one or more RF components between the on-state and the off-state including switching the one or more RF components from the on-state to the off-state based on determination that the at least one detection criterion is not met, and switching the one or more RF components from the off-state to the on-state after an off-state period, wherein a duration of the off-state period is based at least on a preamble duration of the frame preamble; and to repeat switching the one or more RF components between the on-state and the off-state until the frame preamble is detected by the preamble detector.
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公开(公告)号:US20190132154A1
公开(公告)日:2019-05-02
申请号:US16233395
申请日:2018-12-27
申请人: INTEL CORPORATION
发明人: Assaf Gurevitz , Oren Kaidar , Rafi Ben-Tal , Elad Meir , Hagay Barel
摘要: For example, a wireless communication receiver may be configured to switch one or more RF components of the receiver between an on-state and an off-state based on at least one detection criterion for preamble detection of a frame preamble by a preamble detector of the receiver, switching the one or more RF components between the on-state and the off-state including switching the one or more RF components from the on-state to the off-state based on determination that the at least one detection criterion is not met, and switching the one or more RF components from the off-state to the on-state after an off-state period, wherein a duration of the off-state period is based at least on a preamble duration of the frame preamble; and to repeat switching the one or more RF components between the on-state and the off-state until the frame preamble is detected by the preamble detector.
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公开(公告)号:US20160109925A1
公开(公告)日:2016-04-21
申请号:US14978340
申请日:2015-12-22
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号: G06F1/32
CPC分类号: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.
摘要翻译: 提供了一种芯片系统(SoC),包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送,根端口包括电空闲(EI)出口检测电路和参考时钟源。 根端口支持第一链路状态,其中根端口的参考时钟源和EI出口检测电路被禁用,但保持共模电压,第二链路状态,其中参考时钟源和EI退出检测 电路被禁用,并且不保持共模电压。 根据服务等待时间要求小于阈值,根据服务等待时间要求大于或等于阈值,根端口转换到第一链路状态。
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公开(公告)号:US20220083109A1
公开(公告)日:2022-03-17
申请号:US17384971
申请日:2021-07-26
申请人: Intel Corporation
发明人: Raanan Sover , Eytan Mann , Rafi Ben-Tal , Richard S. Perry
摘要: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.
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公开(公告)号:US11073873B1
公开(公告)日:2021-07-27
申请号:US16829524
申请日:2020-03-25
申请人: Intel Corporation
发明人: Raanan Sover , Eytan Mann , Rafi Ben-Tal , Richard S Perry
IPC分类号: G06F1/18 , H05K7/14 , H01L23/538
摘要: An electronic device may include a substrate having a substrate body. The electronic device may include a first interconnect region, for example located proximate to a first end of the substrate. The first interconnect region may extend from the substrate body. The first interconnect region may include a first set of interconnects, and the first set of interconnects may be located proximate to the substrate body. The first interconnect region may include a second set of interconnects, and the second set of interconnects may be located remote from the substrate body. The second set of interconnects may be physically separated from the first set of interconnects, for example by an inactive region. The first set of interconnects may be located between the inactive region and the substrate body.
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公开(公告)号:US09367116B2
公开(公告)日:2016-06-14
申请号:US14978340
申请日:2015-12-22
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
CPC分类号: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.
摘要翻译: 提供了一种芯片系统(SoC),包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送,根端口包括电空闲(EI)出口检测电路和参考时钟源。 根端口支持第一链路状态,其中根端口的参考时钟源和EI出口检测电路被禁用,但保持共模电压,第二链路状态,其中参考时钟源和EI退出检测 电路被禁用,并且不保持共模电压。 根据服务等待时间要求小于阈值,根据服务等待时间要求大于或等于阈值,根端口转换到第一链路状态。
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公开(公告)号:US09280198B2
公开(公告)日:2016-03-08
申请号:US14148530
申请日:2014-01-06
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
CPC分类号: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译: 一种降低平台空闲链路功率的方法和装置。 在本发明的一个实施例中,主机及其在平台中的耦合端点各自具有低功率空闲链路状态,其允许在主机及其耦合的端点中禁用高速链路电路。 这允许平台减少其空闲功率,因为在本发明的一个实施例中,主机及其耦合端点能够关闭其高速链路电路。
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公开(公告)号:US20140310543A1
公开(公告)日:2014-10-16
申请号:US14148530
申请日:2014-01-06
申请人: Intel Corporation
发明人: Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsake , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号: G06F1/32
CPC分类号: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译: 一种降低平台空闲链路功率的方法和装置。 在本发明的一个实施例中,主机及其在平台中的耦合端点各自具有低功率空闲链路状态,其允许在主机及其耦合的端点中禁用高速链路电路。 这允许平台减少其空闲功率,因为在本发明的一个实施例中,主机及其耦合端点能够关闭其高速链路电路。
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