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公开(公告)号：US20240354254A1
公开(公告)日：2024-10-24
申请号：US18759068
申请日：2024-06-28
发明人： Richard C. Murphy
IPC分类号： G06F12/0864 , G06F9/30 , G06F12/0811 , G06F12/084 , G06F12/0895 , G11C7/10 , G11C11/4091 , G11C11/4096 , G11C11/4094 , G11C19/00
CPC分类号： G06F12/0864 , G06F9/30036 , G06F12/0811 , G06F12/084 , G06F12/0895 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G06F2212/1012 , G06F2212/1044 , G06F2212/283 , G06F2212/6032 , G11C11/4094 , G11C19/00
摘要： The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
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公开(公告)号：US12127084B2
公开(公告)日：2024-10-22
申请号：US18380515
申请日：2023-10-16
发明人： Aaron P. Boehm
摘要： Apparatuses, systems, and methods related to accessing a memory resource at one or more physically remote entities are described. A system accessing a memory resource at one or more physically remote entities may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first vehicle configured to determine that a processing capability or a memory capacity, or both, at the first vehicle is insufficient to perform a processing operation at the first vehicle, identify additional processing resources or additional memory capacity, or both, at a second vehicle that is in wireless communication with the first vehicle based at least in part on determining that the processing capability or the memory capacity, or both, at the first vehicle is insufficient, and perform the processing operation at the first vehicle using the additional processing resources or the additional memory capacity, or both.
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公开(公告)号：US20240348268A1
公开(公告)日：2024-10-17
申请号：US18622194
申请日：2024-03-29
发明人： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
CPC分类号： H03M13/45 , G06F9/38 , G06F11/1048 , H03M13/611
摘要： Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US20240347505A1
公开(公告)日：2024-10-17
申请号：US18633330
申请日：2024-04-11
发明人： Sui Chi Huang
IPC分类号： H01L25/065 , H01L21/67 , H01L23/34 , H01L23/40
CPC分类号： H01L25/0652 , H01L21/67098 , H01L23/34 , H01L23/4012 , H01L2225/06589
摘要： A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.
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公开(公告)号：US20240334703A1
公开(公告)日：2024-10-03
申请号：US18738970
申请日：2024-06-10
发明人： Anilkumar Chandolu , Indra V. Chary
摘要： Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.
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公开(公告)号：US20240319909A1
公开(公告)日：2024-09-26
申请号：US18679895
申请日：2024-05-31
发明人： Frank F. Ross
IPC分类号： G06F3/06 , G06F11/20 , G06F12/0868 , G06F12/0897 , G06F13/16 , G11C7/10
CPC分类号： G06F3/0655 , G06F3/0635 , G06F3/0679 , G06F3/0688 , G06F11/201 , G06F12/0868 , G06F12/0897 , G06F13/1668 , G11C7/1075
摘要： The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
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公开(公告)号：US12099639B2
公开(公告)日：2024-09-24
申请号：US17482821
申请日：2021-09-23
CPC分类号： G06F21/79 , G06F21/81 , H04L9/0643
摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.
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公开(公告)号：US20240303194A1
公开(公告)日：2024-09-12
申请号：US18626212
申请日：2024-04-03
IPC分类号： G06F12/0806 , H04L5/00 , H04L27/14
CPC分类号： G06F12/0806 , H04L5/0007 , H04L27/14
摘要： Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.
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公开(公告)号：US20240296125A1
公开(公告)日：2024-09-05
申请号：US18662743
申请日：2024-05-13
CPC分类号： G06F12/10 , G11C16/0483 , G11C16/10 , G11C16/26 , G06F2212/657 , G11C2216/14
摘要： Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.
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10.发明公开公开(公告)号：US20240289219A1
公开(公告)日：2024-08-29
申请号：US18652714
申请日：2024-05-01
CPC分类号： G06F11/1068 , G06F11/076 , G11C13/0026 , G11C13/0028 , G06F2201/88
摘要： An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
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