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    Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode
    3.
    发明授权
    Semiconductor memory device including programmable output pin determining unit and method of reading the same during test mode 有权
    半导体存储器件包括可编程输出引脚确定单元及其在测试模式下读取的方法

    公开(公告)号：US06252805B1

    公开(公告)日：2001-06-26

    申请号：US09540988

    申请日：2000-03-31

    申请人： Byung-se So ,  Jin-ho So

    发明人： Byung-se So ,  Jin-ho So

    IPC分类号： G11C700

    CPC分类号： G11C29/38 ,  G11C29/40

    摘要： A semiconductor memory device is disclosed that programmably varies an output pin transmitting output data from a comparator during a test mode. Also disclosed is a read method for the test mode. The semiconductor memory device includes a comparator that compares a plurality of output data read from the memory cell array and an output pin determining unit that programmably varies a pin transmitting an output of the comparator during the test mode. Thus, when multiple semiconductor memory devices are installed in a single memory module, the output pins of the semiconductor memory devices are variously determined using the output pin determining unit so that data can be simultaneously read from more than one semiconductor memory device at a time during a test of a memory module, to thereby reduce the module test time.

    摘要翻译： 公开了一种半导体存储器件，其可编程地改变在测试模式期间从比较器发送输出数据的输出引脚。 还公开了用于测试模式的读取方法。 半导体存储器件包括比较器，其比较从存储单元阵列读出的多个输出数据和输出引脚确定单元，该输出引脚确定单元在测试模式期间可编程地改变传输比较器的输出的引脚。 因此，当将多个半导体存储器件安装在单个存储器模块中时，使用输出引脚确定单元来不同地确定半导体存储器件的输出引脚，使得可以在多于一个半导体存储器件的同时从多个半导体存储器件读取数据 对内存模块进行测试，从而减少模块测试时间。

    High-speed disturb testing method and word line decoder in semiconductor memory device
    4.
    发明授权
    High-speed disturb testing method and word line decoder in semiconductor memory device 失效
    半导体存储器件中的高速干扰测试方法和字线解码器

    公开(公告)号：US5856982A

    公开(公告)日：1999-01-05

    申请号：US773787

    申请日：1996-12-24

    申请人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

    发明人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/10 ,  G11C29/50

    CPC分类号： G11C29/10

    摘要： A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.

    摘要翻译： 公开了一种用于半导体存储器件的高速干扰测试方法，包括以下步骤：（a）将第一条数据写入存储单元阵列中的所有存储单元; （b）读取并确认写在存储单元阵列的每个存储单元中的第一段数据; （c）在连接到所述多个干扰字线的所有存储单元中写入第二片数据; （d）读取并确认来自所有存储单元的第二件数据（e）将干扰字线的模式固定为测试模式; （f）在与所述多个干扰字线连接的所有存储单元中重复写入第二片数据; （g）将测试模式更改为正常模式; （h）刷新所有的记忆单元; （i）从位于所选择的多个干扰字线附近的字线读取并确认第一片数据; （j）在连接到所述多个干扰字线的所有存储单元中写入第一片数据; （k）重复步骤（3）至（10），从而逐个地对所有字线进行干扰; 和（l）读取和确认来自存储单元阵列的第一片数据。

    Memory module with improved data bus performance
    7.
    发明授权
    Memory module with improved data bus performance 有权

    公开(公告)号：US06772262B1

    公开(公告)日：2004-08-03

    申请号：US09777446

    申请日：2001-02-06

    申请人： Myun-joo Park ,  Byung-se So

    发明人： Myun-joo Park ,  Byung-se So

    IPC分类号： G11C800

    CPC分类号： H05K1/0216 ,  G06F13/1684 ,  G11C5/04 ,  G11C5/06 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2203/1572

    摘要： A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

    Signal transmission circuits that use multiple input signals to generate a respective transmit signal
    8.
    发明授权
    Signal transmission circuits that use multiple input signals to generate a respective transmit signal 失效
    信号传输电路使用多个输入信号来产生相应的发射信号

    公开(公告)号：US07049849B2

    公开(公告)日：2006-05-23

    申请号：US10794680

    申请日：2004-03-05

    申请人： Byung-se So ,  Ga-pyo Nam

    发明人： Byung-se So ,  Ga-pyo Nam

    IPC分类号： H03K19/175

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0276

    摘要： A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals, the first transmit signal being transmitted from the integrated circuit device. A first conductive line is electrically coupled to the first driver circuit and conducts the first transmit signal. A second driver circuit generates a second transmit signal in response to the first transmit signal and a third input signal, the second transmit signal being transmitted from the integrated circuit device. A second conductive line is electrically coupled to the second driver circuit and conducts the second transmit data signal. Related methods are also disclosed.

    摘要翻译： 在集成电路器件之间传导信号的传输电路包括：第一驱动器电路，其响应于第一和第二输入信号产生第一发射信号，第一发射信号从集成电路器件传输。 第一导电线电耦合到第一驱动电路并传导第一发射信号。 第二驱动电路响应于第一发送信号和第三输入信号产生第二发送信号，第二发送信号从集成电路装置发送。 第二导电线电耦合到第二驱动器电路并传导第二发射数据信号。 还公开了相关方法。

    Signal transmission circuits that use multiple input signals to generate a respective transmit signal and methods of operating the same
    9.
    发明授权
    Signal transmission circuits that use multiple input signals to generate a respective transmit signal and methods of operating the same 失效
    使用多个输入信号产生相应发射信号的信号传输电路及其操作方法

    公开(公告)号：US06714595B1

    公开(公告)日：2004-03-30

    申请号：US09426609

    申请日：1999-10-26

    申请人： Byung-se So ,  Ga-pyo Nam

    发明人： Byung-se So ,  Ga-pyo Nam

    IPC分类号： H04L2510

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0276

    摘要： A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals, the first transmit signal being transmitted from the integrated circuit device. A first conductive line is electrically coupled to the first driver circuit and conducts the first transmit signal. A second driver circuit generates a second transmit signal in response to the first transmit signal and a third input signal, the second transmit signal being transmitted from the integrated circuit device. A second conductive line is electrically coupled to the second driver circuit and conducts the second transmit data signal. Related methods are also disclosed.

    摘要翻译： 在集成电路器件之间传导信号的传输电路包括：第一驱动器电路，其响应于第一和第二输入信号产生第一发射信号，第一发射信号从集成电路器件传输。 第一导电线电耦合到第一驱动电路并传导第一发射信号。 第二驱动电路响应于第一发送信号和第三输入信号产生第二发送信号，第二发送信号从集成电路装置发送。 第二导电线电耦合到第二驱动器电路并传导第二发射数据信号。 还公开了相关方法。

    Memory module with improved data bus performance
    10.
    发明授权
    Memory module with improved data bus performance 有权
    内存模块具有改进的数据总线性能

    公开(公告)号：US06990543B2

    公开(公告)日：2006-01-24

    申请号：US10883488

    申请日：2004-07-01

    申请人： Myun-joo Park ,  Byung-se So

    发明人： Myun-joo Park ,  Byung-se So

    IPC分类号： G11C8/00

    CPC分类号： H05K1/0216 ,  G06F13/1684 ,  G11C5/04 ,  G11C5/06 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2203/1572

    摘要： A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

    摘要翻译： 存储器模块能够构成可以减少整个通道的长度的短循环形式的存储器总线系统。 结果，该系统适用于高速操作，并且可以减少制造诸如板和模块连接器的系统的成本。 存储器模块包括位于存储器模块的前部和后侧的一侧中的多个突片，用于通过系统板上的连接器互连，用于连接两个不同信号层的多个通孔 存储器模块和多个数据总线通过每个通孔从存储器模块的前面的突出部延伸到存储器模块的后部上的突出部。 至少一个存储器件连接到每个数据总线。 优选地，每个数据总线形成为垂直于其上形成有突片的存储器模块的一侧。