公开(公告)号：US06754112B2

公开(公告)日：2004-06-22

申请号：US10074309

申请日：2002-02-11

申请人： Young-man Ahn ,  Jin-ho So ,  Byung-se So ,  Seung-jin Seo

发明人： Young-man Ahn ,  Jin-ho So ,  Byung-se So ,  Seung-jin Seo

IPC分类号： G11C722

CPC分类号： G11C7/1093 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

摘要翻译： 集成电路装置包括延迟电路，其被配置为延迟时钟信号，并且还被配置为响应于延迟的时钟信号和输入数据信号而产生输出数据信号。 多个设备被配置为响应于时钟信号分别接收输出数据信号。

公开(公告)号：US06944737B2

公开(公告)日：2005-09-13

申请号：US10094448

申请日：2002-03-08

申请人： Young-man Ahn ,  Jin-ho So ,  Byung-se So

发明人： Young-man Ahn ,  Jin-ho So ,  Byung-se So

IPC分类号： G11C29/00 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/14 ,  G06F12/00

CPC分类号： G11C29/12015 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/1201 ,  G11C29/14

摘要： Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

摘要翻译： 提供了测试存储器模块的存储器模块和方法，其包括响应于具有存储器时钟频率和数据缓冲器的存储器时钟信号的至少一个存储器件。 数据缓冲器响应于在正常操作模式期间具有与存储器时钟频率不同的第一缓冲时钟频率的缓冲时钟信号，并且具有在测试模式期间等于存储器时钟频率的第二缓冲时钟频率 操作。

公开(公告)号：US06252805B1

公开(公告)日：2001-06-26

申请号：US09540988

申请日：2000-03-31

申请人： Byung-se So ,  Jin-ho So

发明人： Byung-se So ,  Jin-ho So

IPC分类号： G11C700

CPC分类号： G11C29/38 ,  G11C29/40

摘要： A semiconductor memory device is disclosed that programmably varies an output pin transmitting output data from a comparator during a test mode. Also disclosed is a read method for the test mode. The semiconductor memory device includes a comparator that compares a plurality of output data read from the memory cell array and an output pin determining unit that programmably varies a pin transmitting an output of the comparator during the test mode. Thus, when multiple semiconductor memory devices are installed in a single memory module, the output pins of the semiconductor memory devices are variously determined using the output pin determining unit so that data can be simultaneously read from more than one semiconductor memory device at a time during a test of a memory module, to thereby reduce the module test time.

摘要翻译： 公开了一种半导体存储器件，其可编程地改变在测试模式期间从比较器发送输出数据的输出引脚。 还公开了用于测试模式的读取方法。 半导体存储器件包括比较器，其比较从存储单元阵列读出的多个输出数据和输出引脚确定单元，该输出引脚确定单元在测试模式期间可编程地改变传输比较器的输出的引脚。 因此，当将多个半导体存储器件安装在单个存储器模块中时，使用输出引脚确定单元来不同地确定半导体存储器件的输出引脚，使得可以在多于一个半导体存储器件的同时从多个半导体存储器件读取数据 对内存模块进行测试，从而减少模块测试时间。

公开(公告)号：US5856982A

公开(公告)日：1999-01-05

申请号：US773787

申请日：1996-12-24

申请人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

发明人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/10 ,  G11C29/50

CPC分类号： G11C29/10

摘要： A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.

摘要翻译： 公开了一种用于半导体存储器件的高速干扰测试方法，包括以下步骤：（a）将第一条数据写入存储单元阵列中的所有存储单元; （b）读取并确认写在存储单元阵列的每个存储单元中的第一段数据; （c）在连接到所述多个干扰字线的所有存储单元中写入第二片数据; （d）读取并确认来自所有存储单元的第二件数据（e）将干扰字线的模式固定为测试模式; （f）在与所述多个干扰字线连接的所有存储单元中重复写入第二片数据; （g）将测试模式更改为正常模式; （h）刷新所有的记忆单元; （i）从位于所选择的多个干扰字线附近的字线读取并确认第一片数据; （j）在连接到所述多个干扰字线的所有存储单元中写入第一片数据; （k）重复步骤（3）至（10），从而逐个地对所有字线进行干扰; 和（l）读取和确认来自存储单元阵列的第一片数据。

公开(公告)号：US20080180120A1

公开(公告)日：2008-07-31

申请号：US11959881

申请日：2007-12-19

申请人： Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

发明人： Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

IPC分类号： G01R1/067

CPC分类号： G01R1/07342

摘要： A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

摘要翻译： 用于将半导体器件连接到测试设备的探针卡包括其中形成电布线图案的印刷电路板（PCB），固定在PCB的上表面上以将测试设备连接到PCB的第一连接器，探针 连接到半导体器件的电极焊盘，以及柔性PCB（FPCB），以将PCB连接到探针。 因此，能够提高信号传递特性，能够降低测试费用，降低接地噪声。

公开(公告)号：US07990168B2

公开(公告)日：2011-08-02

申请号：US12708976

申请日：2010-02-19

申请人： Jong-hoon Kim ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

发明人： Jong-hoon Kim ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

IPC分类号： G01R31/00 ,  G01R1/067

CPC分类号： G01R1/07342

摘要： A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

摘要翻译： 用于将半导体器件连接到测试设备的探针卡包括其中形成电布线图案的印刷电路板（PCB），固定在PCB的上表面上以将测试设备连接到PCB的第一连接器，探针 连接到半导体器件的电极焊盘，以及柔性PCB（FPCB），以将PCB连接到探针。 因此，能够提高信号传递特性，能够降低测试费用，降低接地噪声。

公开(公告)号：US20100141289A1

公开(公告)日：2010-06-10

申请号：US12708976

申请日：2010-02-19

申请人： Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

发明人： Jong-hoon KIM ,  Hyun-ae Lee ,  Jin-ho So ,  Kwang-soo Park

IPC分类号： G01R31/02

CPC分类号： G01R1/07342

摘要： A probe card to connect a semiconductor device to test equipment includes a Printed Circuit Board (PCB) in which an electrical wiring pattern is formed, a first connector fixed on an upper surface of the PCB to connect the test equipment to the PCB, probe needles connected to electrode pads of the semiconductor device, and a Flexible PCB (FPCB) to connect the PCB to the probe needles. Accordingly, a signal transmission characteristic can be enhanced, test expenses can be reduced, and ground noise can be reduced.

摘要翻译： 用于将半导体器件连接到测试设备的探针卡包括其中形成电布线图案的印刷电路板（PCB），固定在PCB的上表面上以将测试设备连接到PCB的第一连接器，探针 连接到半导体器件的电极焊盘，以及柔性PCB（FPCB），以将PCB连接到探针。 因此，能够提高信号传递特性，能够降低测试费用，降低接地噪声。