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发明授权
US06944737B2 Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode 有权
具有根据操作模式在不同时钟频率下操作的缓冲时钟的存储器模块和方法

Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode
摘要：
Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.
摘要（中）：

提供了测试存储器模块的存储器模块和方法，其包括响应于具有存储器时钟频率和数据缓冲器的存储器时钟信号的至少一个存储器件。 数据缓冲器响应于在正常操作模式期间具有与存储器时钟频率不同的第一缓冲时钟频率的缓冲时钟信号，并且具有在测试模式期间等于存储器时钟频率的第二缓冲时钟频率 操作。

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