知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.022 秒)

    Multi-chip package for reducing parasitic load of pin
    2.
    发明授权
    Multi-chip package for reducing parasitic load of pin 有权
    用于减少引脚寄生负载的多芯片封装

    公开(公告)号：US07566958B2

    公开(公告)日：2009-07-28

    申请号：US11589192

    申请日：2006-10-30

    申请人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    发明人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    IPC分类号： H01L23/02

    CPC分类号： H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

    摘要翻译： 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

    Memory module and method of testing the same
    3.
    发明授权
    Memory module and method of testing the same 有权
    内存模块和测试方法相同

    公开(公告)号：US07219274B2

    公开(公告)日：2007-05-15

    申请号：US10831702

    申请日：2004-04-23

    申请人： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

    发明人： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

    IPC分类号： G11C29/04 ,  G11C29/48

    CPC分类号： G11C29/14 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

    摘要： A memory module, including a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.

    摘要翻译： 一种存储器模块，包括用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出 正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。

    Apparatus and method for testing circuit characteristics by using eye mask
    4.
    发明申请
    Apparatus and method for testing circuit characteristics by using eye mask 有权
    使用眼罩测试电路特性的装置和方法

    公开(公告)号：US20070018637A1

    公开(公告)日：2007-01-25

    申请号：US11490984

    申请日：2006-07-21

    申请人： Woo-Seop Kim ,  Jun-Young Park ,  Sung-Je Hong ,  Sung-Bum Cho ,  Byung-Se So ,  Hyun-Chul Kang

    发明人： Woo-Seop Kim ,  Jun-Young Park ,  Sung-Je Hong ,  Sung-Bum Cho ,  Byung-Se So ,  Hyun-Chul Kang

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3171 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50012 ,  G11C29/56

    摘要： A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.

    摘要翻译： 一种能够通过分析在测试装置中产生的眼罩和从半导体器件的I / O电路输出的测试信号的波形来检测半导体器件的输入/输出（I / O）电路特性的测试装置。 所述测试装置包括与彼此相反相位的一个或多个时钟信号同步地生成眼罩的眼罩发生器，从眼罩发生器接收眼罩并将测试信号与眼罩相比较的误差检测器 以确定半导体器件中是否发生错误;以及误差信号输出单元，其接收来自误差检测器的误差检测信号，并响应于误差检测信号产生误差信号。 特别地，眼罩发生器包括正弦波发生器，其与一个或多个时钟信号同步地产生彼此相反相位的一个或多个正弦波，以及限制器电路，其接收正弦波并通过调整产生眼罩 正弦波的幅度。

    Multi-chip package for reducing parasitic load of pin
    5.
    发明授权
    Multi-chip package for reducing parasitic load of pin 有权
    用于减少引脚寄生负载的多芯片封装

    公开(公告)号：US07148563B2

    公开(公告)日：2006-12-12

    申请号：US10722159

    申请日：2003-11-26

    申请人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    发明人： Byung-Se So ,  Dong-Ho Lee ,  Hyun-Soon Jang

    IPC分类号： H01L23/02

    CPC分类号： H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.

    摘要翻译： 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接从多芯片封装的相应引脚接收输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。