公开(公告)号：US20080106966A1

公开(公告)日：2008-05-08

申请号：US11979424

申请日：2007-11-02

申请人： Hwan-Wook Park ,  Woo-Seop Kim

发明人： Hwan-Wook Park ,  Woo-Seop Kim

IPC分类号： G11C11/00 ,  G05F1/10

CPC分类号： G11C5/143

摘要： A power-up/power-down detecting circuit may include a power detecting circuit, a selecting circuit, and a determining circuit. The power detecting circuit may generate a plurality of detection signals based on a plurality of sensing signals corresponding to currents flowing through a plurality of function blocks. The selecting circuit may generate a plurality of selection signals. The determining circuit may generate a power-up completion signal and a power-down completion signal. A semiconductor device having the power-up/power-down detecting circuit may determine in real time the power-up time and the power-down time.

摘要翻译： 上电/断电检测电路可以包括功率检测电路，选择电路和确定电路。 功率检测电路可以基于与流过多个功能块的电流相对应的多个感测信号来生成多个检测信号。 选择电路可以产生多个选择信号。 确定电路可以产生上电完成信号和掉电完成信号。 具有上电/断电检测电路的半导体器件可以实时地确定上电时间和断电时间。

公开(公告)号：US20110193214A1

公开(公告)日：2011-08-11

申请号：US13089120

申请日：2011-04-18

申请人： Soo-Jin Paek ,  Woo-Seop Kim ,  Ki-Sung Kim

发明人： Soo-Jin Paek ,  Woo-Seop Kim ,  Ki-Sung Kim

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/367 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/0401

摘要： A semiconductor package having a structure in which heat produced in the interior of the package is effectively spread to the outside of the package is provided. The semiconductor package includes one or more semiconductor chips, one or more substrates (PCBs) having the semiconductor chips respectively attached thereto, a plurality of conductive balls such as a plurality of solder balls to provide voltages and signals to the one or more semiconductor chips, and a heat sink positioned to spread heat produced in the interior of the package to the outside and directly connected to at least one of the plurality of solder balls.

摘要翻译： 提供了一种半导体封装，其具有将封装内部产生的热有效地扩散到封装外部的结构。 半导体封装包括一个或多个半导体芯片，分别具有半导体芯片的一个或多个基板（PCB），多个导电球，例如多个焊球，以向一个或多个半导体芯片提供电压和信号， 以及散热器，定位成将包装内部产生的热量扩散到外部并直接连接到多个焊球中的至少一个。

公开(公告)号：US07656181B2

公开(公告)日：2010-02-02

申请号：US11490984

申请日：2006-07-21

申请人： Woo-Seop Kim ,  Jun-Young Park ,  Sung-Je Hong ,  Sung-Bum Cho ,  Byung-Se So ,  Hyun-Chul Kang

发明人： Woo-Seop Kim ,  Jun-Young Park ,  Sung-Je Hong ,  Sung-Bum Cho ,  Byung-Se So ,  Hyun-Chul Kang

IPC分类号： G01R31/26

CPC分类号： G01R31/3171 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50012 ,  G11C29/56

摘要： A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.

摘要翻译： 一种能够通过分析在测试装置中产生的眼罩和从半导体器件的I / O电路输出的测试信号的波形来检测半导体器件的输入/输出（I / O）电路特性的测试装置。 所述测试装置包括与彼此相反相位的一个或多个时钟信号同步地生成眼罩的眼罩发生器，从眼罩发生器接收眼罩并将测试信号与眼罩相比较的误差检测器 以确定半导体器件中是否发生错误;以及误差信号输出单元，其接收来自误差检测器的误差检测信号，并响应于误差检测信号产生误差信号。 特别地，眼罩发生器包括正弦波发生器，其与一个或多个时钟信号同步地产生彼此相反相位的一个或多个正弦波，以及限制器电路，其接收正弦波并通过调整产生眼罩 正弦波的幅度。

公开(公告)号：US07555686B2

公开(公告)日：2009-06-30

申请号：US11483753

申请日：2006-07-10

申请人： Woo-seop Kim

发明人： Woo-seop Kim

IPC分类号： G01R31/28

CPC分类号： G11C29/56 ,  G11C29/56012 ,  G11C2029/5602

摘要： Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and serially outputs the test pattern data to the outside at a second speed that is different from the first speed.

摘要翻译： 提供半导体器件，测试板以及用于测试半导体器件的测试系统和方法。 半导体器件包括以第一速度串行输入测试图案数据的输入端子和一对一对应于输入端子的输出端子，并以第二速度将测试图案数据串行输出到外部 与第一速度不同。

公开(公告)号：US20080106950A1

公开(公告)日：2008-05-08

申请号：US11859824

申请日：2007-09-24

申请人： Jae-wook LEE ,  Hoe-ju CHUNG ,  Woo-seop KIM

发明人： Jae-wook LEE ,  Hoe-ju CHUNG ,  Woo-seop KIM

IPC分类号： G11C7/10

CPC分类号： G11C29/14 ,  G11C2029/5602

摘要： The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bidirectional communications with a host. But during a test mode, a first channel is used to communicate with the ATE in one direction, and a second channel is used to communicate with the ATE in the opposite direction. The present invention also provides a memory module and a method for controlling the high-speed memory device.

摘要翻译： 本发明提供一种可以使用现有的低速自动测试设备（ATE）容易地测试的高速存储器件。 在本发明的实施例中，存储器装置包括两个通道。 在与主机的正常通信期间，一个通道用于与主机的双向通信。 但在测试模式下，第一个通道用于与ATE在一个方向进行通信，第二个通道用于与ATE在相反的方向进行通信。 本发明还提供了一种用于控制高速存储器件的存储器模块和方法。

公开(公告)号：US20070173097A1

公开(公告)日：2007-07-26

申请号：US11656598

申请日：2007-01-23

申请人： Woo-Seop Kim

发明人： Woo-Seop Kim

IPC分类号： H01R13/15

CPC分类号： H01L22/32 ,  G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A socket for an electrical tester is disclosed. The socket includes a first contact board being arranged at a bottom side of a test object, and a second contact board being arranged at a top side of the test object. The first contact board includes a first contact member and a first conductive connection member, wherein the first contact member is electrically connected to a bottom connection terminal formed on the bottom side of the test object, and the first conductive connection member is isolated from the test object. The second contact board includes a second contact member, wherein the second contact member is electrically connected to the first conductive connection member and a top connection terminal formed on a top side of the test object, respectively. Therefore, the socket can have a simple configuration for providing the test current.

摘要翻译： 公开了一种用于电测试器的插座。 插座包括布置在测试对象的底侧的第一接触板和布置在测试对象的顶侧的第二接触板。 第一接触板包括第一接触构件和第一导电连接构件，其中第一接触构件电连接到形成在被测物体的底侧上的底部连接端子，并且第一导电连接构件与测试隔离 目的。 第二接触板包括第二接触构件，其中第二接触构件分别电连接到第一导电连接构件和形成在测试对象的顶侧上的顶部连接端子。 因此，插座可以具有用于提供测试电流的简单配置。

公开(公告)号：US20060126403A1

公开(公告)日：2006-06-15

申请号：US11243369

申请日：2005-10-04

申请人： Gyung-Su Byun ,  Kyu-Hyoun Kim ,  Woo-Seop Kim

发明人： Gyung-Su Byun ,  Kyu-Hyoun Kim ,  Woo-Seop Kim

IPC分类号： G11C7/10

CPC分类号： G11C29/50008 ,  G11C7/1048 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5006 ,  G11C2207/105

摘要： A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

公开(公告)号：US5856982A

公开(公告)日：1999-01-05

申请号：US773787

申请日：1996-12-24

申请人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

发明人： Byung-se So ,  Jin-ho So ,  Woo-seop Kim ,  Dal-jo Lee

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/10 ,  G11C29/50

CPC分类号： G11C29/10

摘要： A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.

摘要翻译： 公开了一种用于半导体存储器件的高速干扰测试方法，包括以下步骤：（a）将第一条数据写入存储单元阵列中的所有存储单元; （b）读取并确认写在存储单元阵列的每个存储单元中的第一段数据; （c）在连接到所述多个干扰字线的所有存储单元中写入第二片数据; （d）读取并确认来自所有存储单元的第二件数据（e）将干扰字线的模式固定为测试模式; （f）在与所述多个干扰字线连接的所有存储单元中重复写入第二片数据; （g）将测试模式更改为正常模式; （h）刷新所有的记忆单元; （i）从位于所选择的多个干扰字线附近的字线读取并确认第一片数据; （j）在连接到所述多个干扰字线的所有存储单元中写入第一片数据; （k）重复步骤（3）至（10），从而逐个地对所有字线进行干扰; 和（l）读取和确认来自存储单元阵列的第一片数据。

公开(公告)号：US20120025861A1

公开(公告)日：2012-02-02

申请号：US13196380

申请日：2011-08-02

申请人： Hwan Wook PARK ,  Woo Seop KIM ,  Sung Bum CHO

发明人： Hwan Wook PARK ,  Woo Seop KIM ,  Sung Bum CHO

IPC分类号： G01R31/00

CPC分类号： G01R1/045 ,  G01R1/0466

摘要： A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor.

摘要翻译： 提供测试设备。 测试装置包括发送电源电压的第一通孔，发送接地电压的第二通孔，包括用于发送多个测试信号的多个测试信号通孔的测试板，设置在测试的上部的电容器 并连接在第一通孔和第二通孔之间，以及将被测器件（DUT）与测试板电连接的测试插座。 测试插座包括：第一区域，包括与测试板邻接的平坦的下表面，包括不平坦的下表面的第二区域;多个第一接触器，其布置在第一区域中并连接到多个通孔;以及两个 第二接触器，其布置在第二区域中并且连接到电容器的两个端子。

公开(公告)号：US07512024B2

公开(公告)日：2009-03-31

申请号：US11859824

申请日：2007-09-24

申请人： Jae-wook Lee ,  Hoe-ju Chung ,  Woo-seop Kim

发明人： Jae-wook Lee ,  Hoe-ju Chung ,  Woo-seop Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C2029/5602

摘要： The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bi-directional communications with a host. But during a test mode, a first channel is used to communicate with the ATE in one direction, and a second channel is used to communicate with the ATE in the opposite direction. The present invention also provides a memory module and a method for controlling the high-speed memory device.

摘要翻译： 本发明提供一种可以使用现有的低速自动测试设备（ATE）容易地测试的高速存储器件。 在本发明的实施例中，存储器装置包括两个通道。 在与主机的正常通信期间，一个信道用于与主机的双向通信。 但在测试模式下，第一个通道用于与ATE在一个方向进行通信，第二个通道用于与ATE在相反的方向进行通信。 本发明还提供了一种用于控制高速存储器件的存储器模块和方法。