公开(公告)号：US07512024B2

公开(公告)日：2009-03-31

申请号：US11859824

申请日：2007-09-24

申请人： Jae-wook Lee ,  Hoe-ju Chung ,  Woo-seop Kim

发明人： Jae-wook Lee ,  Hoe-ju Chung ,  Woo-seop Kim

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C2029/5602

摘要： The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bi-directional communications with a host. But during a test mode, a first channel is used to communicate with the ATE in one direction, and a second channel is used to communicate with the ATE in the opposite direction. The present invention also provides a memory module and a method for controlling the high-speed memory device.

摘要翻译： 本发明提供一种可以使用现有的低速自动测试设备（ATE）容易地测试的高速存储器件。 在本发明的实施例中，存储器装置包括两个通道。 在与主机的正常通信期间，一个信道用于与主机的双向通信。 但在测试模式下，第一个通道用于与ATE在一个方向进行通信，第二个通道用于与ATE在相反的方向进行通信。 本发明还提供了一种用于控制高速存储器件的存储器模块和方法。

公开(公告)号：US08054663B2

公开(公告)日：2011-11-08

申请号：US12264356

申请日：2008-11-04

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

摘要翻译： 多芯片封装存储器包括产生关于参考处理变化定义的至少一个参考信号的接口芯片和经由垂直连接路径电连接到接口芯片的多个存储器芯片，并经由 垂直连接路径，其中堆叠的多个存储器芯片中的每个存储器芯片的特征在于处理变化，并且主动地补偿与参考信号相关的所述处理变化。

公开(公告)号：US07296110B2

公开(公告)日：2007-11-13

申请号：US11071586

申请日：2005-03-04

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/4243

摘要： Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

摘要翻译： 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

公开(公告)号：US08117485B2

公开(公告)日：2012-02-14

申请号：US12379276

申请日：2009-02-18

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F1/12

CPC分类号： G11C29/56012

摘要： Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.

摘要翻译： 提供了一种用于无缝切换的存储器系统。 存储器系统包括第一至第m个芯片，其中m是自然数，以菊链的形式连接并被配置为传输信号和数据中的至少一个，第一至第m个芯片的第（k-1）个芯片 ，其中k是自然数，2＆nlE; k＆nlE; m，被配置为输出与第（k-1）个芯片的第（k-1）个测试数据和第（k-1）个芯片之间的相位差相对应的第（k-1） 第k个芯片的第k个测试数据，第k个芯片包括时钟相位控制单元，其被配置为控制接收到的时钟信号的相位并将相位控制的时钟信号输出为第k个时钟信号，其中 第k个芯片的时钟相位控制单元响应第（k-1）个检测信号输出第k个时钟信号。

公开(公告)号：US07913000B2

公开(公告)日：2011-03-22

申请号：US12186040

申请日：2008-08-05

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

摘要： A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

摘要翻译： 公开了一种使用复合读取缓冲器操作的堆叠式存储装置。 堆叠式存储装置包括具有主缓冲器和多个存储装置的接口装置，每个存储装置具有装置读缓冲器。 还公开了包含一个或多个堆叠存储器装置的系统和执行读取操作的相关方法。

公开(公告)号：US07734967B2

公开(公告)日：2010-06-08

申请号：US11863500

申请日：2007-09-28

申请人： Hoe-ju Chung ,  Yun-sang Lee

发明人： Hoe-ju Chung ,  Yun-sang Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

摘要： A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

摘要翻译： 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的工作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。

公开(公告)号：US20090282280A1

公开(公告)日：2009-11-12

申请号：US12379276

申请日：2009-02-18

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F1/08

CPC分类号： G11C29/56012

摘要： Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.

摘要翻译： 提供了一种用于无缝切换的存储器系统。 存储器系统包括第一至第m个芯片，其中m是自然数，以菊链的形式连接并被配置为传输信号和数据中的至少一个，第一至第m个芯片的第（k-1）个芯片 ，其中k是自然数，2 <= k <= m，被配置为输出与第（k-1）次的第（k-1）个测试数据之间的相位差相对应的第（k-1） 芯片和第k个测试数据，第k个芯片包括时钟相位控制单元，其被配置为控制接收的时钟信号的相位，并输出相位控制的时钟信号作为第k个时钟信号 ，其中第k个芯片的时钟相位控制单元响应于第（k-1）个检测信号输出第k个时钟信号。

公开(公告)号：US08446988B2

公开(公告)日：2013-05-21

申请号：US13280456

申请日：2011-10-25

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： H04L27/06

CPC分类号： H04L25/0264 ,  H04L25/0272

摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

摘要翻译： 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US08261004B2

公开(公告)日：2012-09-04

申请号：US13026462

申请日：2011-02-14

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

摘要： A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

摘要翻译： 公开了一种使用复合读取缓冲器操作的堆叠式存储装置。 堆叠式存储装置包括具有主缓冲器和多个存储装置的接口装置，每个存储装置具有装置读缓冲器。 还公开了包含一个或多个堆叠存储器装置的系统和执行读取操作的相关方法。

公开(公告)号：US07957217B2

公开(公告)日：2011-06-07

申请号：US12266716

申请日：2008-11-07

申请人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

发明人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C5/04

摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。