知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.045 seconds)

    Integrated circuit having spare parts activated by a high-to-low adjustable resistance device
    2.
    发明授权
    Integrated circuit having spare parts activated by a high-to-low adjustable resistance device 失效
    具有由高到低可调电阻器件激活的备件的集成电路

    公开(公告)号：US4399372A

    公开(公告)日：1983-08-16

    申请号：US213846

    申请日：1980-12-08

    Applicant: Masafumi Tanimoto ,  Nobuaki Ieda ,  Masato Wada

    Inventor： Masafumi Tanimoto ,  Nobuaki Ieda ,  Masato Wada

    IPC: G06F12/16 ,  G11C5/00 ,  G11C11/34 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01C7/10 ,  H01C17/26 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/00 ,  H03K19/013 ,  H01L29/04 ,  H03H5/12 ,  H03L3/00

    CPC classification number: G11C29/785 ,  G11C11/34 ,  G11C17/16 ,  G11C5/00 ,  H01C17/267 ,  H01C7/10 ,  H01L27/11803 ,  H03K19/0136

    Abstract: Disclosed is a semiconductor integrated circuit device comprising a semiconductor chip including a plurality of elements constituting multi-functional circuits and a control signal generating circuit incorporated within the semiconductor chip. The control signal generating circuit includes a variable resistance element which irreversibly changes its resistivity when a voltage having a magnitude larger than a specific level, is applied. The variable resistance element is connected in series with a fixed resistor which is further connected in parallel to the output electrodes of a field effect transistor. A control signal is applied to the input terminal of the transistor when the resistance of the variable resistance element is intended to change. An output terminal connected to the connection of the serial connected elements indicates logical "1" or "0" depending on whether the variable resistance element is in the high resistivity state or low resistivity state. In the semiconductor integrated circuit, the output of the control signal generating circuit is transmitted to at least one of the multi-functional circuits, so that it is activated or left deactivated.

    Abstract translation: 公开了一种包括半导体芯片的半导体集成电路器件，该半导体芯片包括构成多功能电路的多个元件和并入该半导体芯片内的控制信号发生电路。 控制信号发生电路包括可变电阻元件，其在施加具有大于特定电平的电压的电压时不可逆地改变其电阻率。 可变电阻元件与固定电阻器串联连接，该固定电阻器进一步与场效应晶体管的输出电极并联连接。 当可变电阻元件的电阻意图改变时，控制信号施加到晶体管的输入端子。 连接到串行连接元件的连接的输出端子根据可变电阻元件是处于高电阻状态还是低电阻状态而指示逻辑“1”或“0”。 在半导体集成电路中，控制信号发生电路的输出被发送到多功能电路中的至少一个，使得其被激活或停用。

    Sensing circuit for memory cells
    3.
    发明授权
    Sensing circuit for memory cells 失效
    存储单元的感应电路

    公开(公告)号：US4070590A

    公开(公告)日：1978-01-24

    申请号：US712708

    申请日：1976-08-09

    Applicant: Nobuaki Ieda ,  Takao Yano

    Inventor： Nobuaki Ieda ,  Takao Yano

    IPC: G11C11/4094 ,  H03K3/356 ,  H03K5/20 ,  G11C11/40 ,  H03K3/286 ,  H03K5/18

    CPC classification number: H03K3/35606 ,  G11C11/4094

    Abstract: A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from each other, and in which power supply transistors are inserted between power sources and the bit lines. When the power supply transistors are turned on, the separation transistors are turned off, so that a signal detection can be performed with little power consumption. Further, in such a case, the bit lines are disconnected from the sensing circuit to thereby enable a high-speed and highly sensitive detecting operation to be stably achieved regardless of the number of memory cells.

    Abstract translation: 一种弱信号检测电路，其中形成有触发电路的感测电路和各自连接有多个1-晶体管型存储单元的位线通过用于将它们彼此分离的分离晶体管互连，其中 电源晶体管插在电源和位线之间。 当电源晶体管导通时，分离晶体管截止，使得能够以很少的功耗进行信号检测。 此外，在这种情况下，位线与感测电路断开，从而能够稳定地实现高速和高灵敏度的检测操作，而与存储单元的数量无关。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06229165B1

    公开(公告)日：2001-05-08

    申请号：US09143510

    申请日：1998-08-28

    Applicant: Tetsushi Sakai ,  Nobuaki Ieda ,  Masayuki Ino ,  Shigeru Nakajima ,  Yukio Akazawa ,  Tsuneo Mano ,  Hiroshi Inokawa

    Inventor： Tetsushi Sakai ,  Nobuaki Ieda ,  Masayuki Ino ,  Shigeru Nakajima ,  Yukio Akazawa ,  Tsuneo Mano ,  Hiroshi Inokawa

    IPC: H01L31062

    CPC classification number: H01L27/1443 ,  H01L27/14812 ,  H01L31/101

    Abstract: This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.

    Abstract translation: 本发明提供一种半导体器件，包括硅层，形成在硅层上的绝缘层，形成在绝缘膜上以将光转换为电信号的第一半导体器件，以及形成在绝缘膜上的第二半导体器件，其中， 在硅层中形成硅区域以遮蔽第二半导体器件，并且在对应于第一半导体器件的硅层的部分中形成有通过除了硅区域之外的硅层延伸到第一半导体器件的光的通孔， 第一和第二半导体器件的下部。

Patent Agency Ranking