公开(公告)号：US5894440A

公开(公告)日：1999-04-13

申请号：US189276

申请日：1994-01-31

Applicant: Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

Inventor： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC classification number: G11C7/06 ,  G11C7/1006 ,  G11C7/1039

Abstract: Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Abstract translation: 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。

公开(公告)号：US5588130A

公开(公告)日：1996-12-24

申请号：US283367

申请日：1994-08-01

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC: G06F12/08 ,  G11C7/10 ,  G06F13/00 ,  G11C15/00

CPC classification number: G06F12/0893 ,  G11C7/1021

Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

公开(公告)号：US5371714A

公开(公告)日：1994-12-06

申请号：US26225

申请日：1993-02-26

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

IPC: G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

Abstract: In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

Abstract translation: 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

公开(公告)号：US5267214A

公开(公告)日：1993-11-30

申请号：US616264

申请日：1990-11-20

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/34

CPC classification number: G11C11/4091 ,  G11C11/4076

Abstract: A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

Abstract translation: 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。

公开(公告)号：US5103426A

公开(公告)日：1992-04-07

申请号：US528511

申请日：1990-05-25

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: H01L21/82 ,  G11C5/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C29/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03M7/00 ,  H03M7/22

CPC classification number: G11C8/12 ,  G11C5/066 ,  G11C29/006

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

公开(公告)号：US5014241A

公开(公告)日：1991-05-07

申请号：US337219

申请日：1989-04-12

Applicant: Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C5/025 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/063 ,  G11C7/14 ,  G11C7/18

Abstract: Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

Abstract translation: 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。

公开(公告)号：US4977542A

公开(公告)日：1990-12-11

申请号：US400898

申请日：1989-08-30

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

IPC: G11C11/401 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C7/14 ,  G11C7/18 ,  G11C8/14

Abstract: An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

Abstract translation: 一种用于在包括扭转位线的存储器结构中提供字线和位线之间的电容耦合补偿的装置。 保持在预定电位的两个虚拟字线形成在一对位线的扭转部分。 在虚拟字线和位线的相应扭转部分设置虚拟单元。 在与位线相交的方向上形成多个字线，并且根据位线对的扭绞部分的位置将字线分成四个字线组。 当选择任意字线时，与所选字线所属的字线组对应的至少一个虚拟字线的电位降低。 因此，通过降低至少一个虚拟字线的电位来补偿由字线的选择引起的位线的电位的上升，使得可以减少读取中的误差。 特殊的单元层布置简化了虚拟单元补偿与电容耦合的扭转位线平衡组合的集成密度的增加。

公开(公告)号：US4855953A

公开(公告)日：1989-08-08

申请号：US158323

申请日：1988-02-19

Applicant: Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10861 ,  G11C11/404 ,  H01L27/10829 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66181

Abstract: A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

Abstract translation: 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

公开(公告)号：US06404691B1

公开(公告)日：2002-06-11

申请号：US08472770

申请日：1995-06-07

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC: G11C700

CPC classification number: G06F12/0893 ,  G11C7/1021

Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Abstract translation: 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。

公开(公告)号：US6075732A

公开(公告)日：2000-06-13

申请号：US334917

申请日：1999-06-17

Applicant: Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC: G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC classification number: G11C29/806 ,  G11C29/781 ,  G11C8/10

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract translation: 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器​​（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。