公开(公告)号：US08274148B2

公开(公告)日：2012-09-25

申请号：US12727565

申请日：2010-03-19

申请人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

发明人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/94 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

摘要翻译： 第一电路元件和第二元件安装成其电极形成表面面向布线层。 与一个面上的布线层一体形成的第一凸块电极基本上贯穿第一绝缘树脂层。 覆盖第一电路元件的元件电极的镀金层和设置在第一凸块电极顶部的镀金层通过Au-Au键合而接合在一起。 与一个面上的布线层一体形成的第二凸块电极基本上贯穿第一绝缘树脂层和第二绝缘树脂层。 覆盖第二电路元件的元件电极的镀金层和设置在第二凸块电极顶部的金镀层通过Au-Au键合而接合在一起。

公开(公告)号：US20100193946A1

公开(公告)日：2010-08-05

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

摘要翻译： 半导体模块包括：绝缘树脂层; 布线层，其设置在绝缘树脂层的一个主表面上，并且包括外部连接区域; 电连接到布线层并且各自形成为从布线层向绝缘树脂层突出的突起电极; 设置在绝缘树脂层的另一个主表面上并且包括连接到凸起电极的器件电极的半导体器件; 以及设置在布线层和绝缘树脂层上以使外部连接区域露出的布线保护层。 在半导体模块中，布线保护层的外边缘部分与半导体器件的外边缘部分接触，从而在侧边缘屏蔽半导体树脂层的至少一部分。

公开(公告)号：US08242598B2

公开(公告)日：2012-08-14

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/48

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

公开(公告)号：US08362611B2

公开(公告)日：2013-01-29

申请号：US12679595

申请日：2008-09-25

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

IPC分类号： H01L23/488

CPC分类号： H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00

摘要： A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.

摘要翻译： 半导体模块具有这样的结构，使得布线层，绝缘树脂层和半导体器件通过将它们压缩在一起而依次堆叠。 在布线层中，各自具有基底和尖端部分的凸起电极设置在分别对应于半导体器件的器件电极的位置。 凸块电极穿透绝缘树脂层并电耦合到相应的器件电极。

公开(公告)号：US08288865B2

公开(公告)日：2012-10-16

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

摘要翻译： 半导体模块包括：绝缘树脂层; 布线层，其设置在绝缘树脂层的一个主表面上，并且包括外部连接区域; 电连接到布线层并且各自形成为从布线层向绝缘树脂层突出的突起电极; 设置在绝缘树脂层的另一个主表面上并且包括连接到凸起电极的器件电极的半导体器件; 以及设置在布线层和绝缘树脂层上以使外部连接区域露出的布线保护层。 在半导体模块中，布线保护层的外边缘部分与半导体器件的外边缘部分接触，从而在侧边缘屏蔽半导体树脂层的至少一部分。

公开(公告)号：US08278566B2

公开(公告)日：2012-10-02

申请号：US12364084

申请日：2009-02-02

申请人： Hajime Kobayashi ,  Yasuyuki Yanase ,  Tetsuya Yamamoto ,  Yoshio Okayama

发明人： Hajime Kobayashi ,  Yasuyuki Yanase ,  Tetsuya Yamamoto ,  Yoshio Okayama

IPC分类号： H05K1/11

摘要： A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.

公开(公告)号：US07989359B2

公开(公告)日：2011-08-02

申请号：US12022812

申请日：2008-01-30

申请人： Yoshio Okayama ,  Yasuyuki Yanase

发明人： Yoshio Okayama ,  Yasuyuki Yanase

IPC分类号： H01L21/31

CPC分类号： H01L21/4832 ,  H01L21/4828 ,  H01L21/561 ,  H01L24/11 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/274 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00014

摘要： A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.

摘要翻译： 准备在其表面上具有半导体器件的电极和图案单元的半导体衬底。 形成铜板，其具有具有凸起的第一主表面和与第一主表面相对的第二主表面，具有沟槽。 通过调整铜板的位置使得图案单元和相应的沟槽具有预定的位置关系，凸块和电极对准，铜板的第一主表面和半导体衬底通过绝缘体压接 层，并且凸块和电极在凸块穿过绝缘层时电连接。 在第二原理表面的一侧形成预定的重新布线图形。

公开(公告)号：US20080203557A1

公开(公告)日：2008-08-28

申请号：US12022487

申请日：2008-01-30

申请人： Tetsuya Yamamoto ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Tetsuro Sawai

发明人： Tetsuya Yamamoto ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Tetsuro Sawai

IPC分类号： H01L23/12 ,  H01L21/44

CPC分类号： H01L21/481 ,  H01L21/4832 ,  H01L21/6835 ,  H01L23/4334 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/274 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05099

摘要： Warp of a circuit device manufactured by the wafer level packaging technology is reduced. A semiconductor substrate used in a circuit device is provided with a circuit device and electrodes connected to the circuit device. A wiring layer having bumps connected to the electrodes is provided on a major surface of the semiconductor substrate. A metal layer is provided on a surface opposite to the major surface of the semiconductor substrate.

摘要翻译： 通过晶片级封装技术制造的电路器件的翘曲减少。 在电路器件中使用的半导体衬底设置有电路器件和连接到电路器件的电极。 在半导体基板的主表面上设置具有与电极连接的突起的布线层。 在与半导体基板的主表面相对的表面上设置有金属层。

公开(公告)号：US08237258B2

公开(公告)日：2012-08-07

申请号：US12394721

申请日：2009-02-27

申请人： Kouichi Saitou ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Kouichi Saitou ,  Yoshio Okayama ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/485

CPC分类号： H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511

摘要： A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.

摘要翻译： 半导体模块包括装置安装板和安装在装置安装板上的半导体装置。 装置安装板包括绝缘树脂层，设置在绝缘树脂层的一个主表面上的布线层和从布线层向绝缘树脂层突出的与布线层电连接的凸起电极。 半导体器件具有分别与半导体衬底和凸起电极相对设置的器件电极。 设置在器件电极上的金属层的表面位于与保护层的表面相同的平面上。

公开(公告)号：US07855452B2

公开(公告)日：2010-12-21

申请号：US12022865

申请日：2008-01-30

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area.The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

摘要翻译： 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。